mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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317 lines
12 KiB
C++
317 lines
12 KiB
C++
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#include "umtrx_regs.hpp"
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#include <uhd/exception.hpp>
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#include <uhd/utils/msg.hpp>
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#include <uhd/utils/safe_call.hpp>
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#include <uhd/transport/vrt_if_packet.hpp>
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#include "umtrx_fifo_ctrl.hpp"
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#include <boost/thread/mutex.hpp>
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#include <boost/thread/thread.hpp>
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#include <boost/asio.hpp> //htonl
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#include <boost/format.hpp>
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using namespace uhd;
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using namespace uhd::transport;
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//command policy flags
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static const size_t POKE32_CMD = (1 << 8);
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static const size_t PEEK32_CMD = 0; //no flag set
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static const size_t TIME_WAIT_CMD = (1 << 9);
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static const size_t SKIP_LATE_CMD = (1 << 10);
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static const double ACK_TIMEOUT = 0.5;
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static const double MASSIVE_TIMEOUT = 10.0; //for when we wait on a timed command
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static const boost::uint32_t FIFO_DEPTH = 64;
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static const boost::uint32_t MAX_SEQS_OUT = FIFO_DEPTH-1;
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#define SPI_DIV SR_SPI_CORE + 0
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#define SPI_CTRL SR_SPI_CORE + 1
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#define SPI_DATA SR_SPI_CORE + 2
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// spi clock rate = master_clock/(div+1)/2
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#define SPI_DIVIDER 16
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class umtrx_fifo_ctrl_impl : public umtrx_fifo_ctrl{
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public:
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umtrx_fifo_ctrl_impl(zero_copy_if::sptr xport, const boost::uint32_t sid, const boost::uint32_t window_size):
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_xport(xport),
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_sid(sid),
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_window_size(std::min(window_size, MAX_SEQS_OUT)),
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_seq_out(0),
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_seq_ack(0),
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_prev_recv_seq(0),
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_total_recv_packets(0),
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_start_of_burst(false),
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_skip_late(false),
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_use_time(false),
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_tick_rate(1.0),
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_timeout(ACK_TIMEOUT)
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{
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UHD_MSG(status) << "fifo_ctrl.window_size = " << _window_size << std::endl;
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while (_xport->get_recv_buff(0.0)){} //flush
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this->set_time(uhd::time_spec_t(0.0));
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this->set_tick_rate(1.0); //something possible but bogus
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this->init_spi();
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}
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~umtrx_fifo_ctrl_impl(void){
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_timeout = ACK_TIMEOUT; //reset timeout to something small
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UHD_SAFE_CALL(
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this->peek32(0); //dummy peek with the purpose of ack'ing all packets
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)
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}
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/*******************************************************************
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* Peek and poke 32 bit implementation
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******************************************************************/
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void poke32(wb_addr_type addr, boost::uint32_t data){
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boost::mutex::scoped_lock lock(_mutex);
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this->send_pkt((addr - SETTING_REGS_BASE)/4, data, POKE32_CMD);
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this->wait_for_ack(_seq_out-_window_size);
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}
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boost::uint32_t peek32(wb_addr_type addr){
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boost::mutex::scoped_lock lock(_mutex);
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this->send_pkt((addr - READBACK_BASE)/4, 0, PEEK32_CMD);
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return this->wait_for_ack(_seq_out);
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}
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/*******************************************************************
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* Peek and poke 16 bit not implemented
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******************************************************************/
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void poke16(wb_addr_type, boost::uint16_t){
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throw uhd::not_implemented_error("poke16 not implemented in fifo ctrl module");
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}
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boost::uint16_t peek16(wb_addr_type){
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throw uhd::not_implemented_error("peek16 not implemented in fifo ctrl module");
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}
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/*******************************************************************
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* FIFO controlled SPI implementation
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******************************************************************/
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void init_spi(void){
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boost::mutex::scoped_lock lock(_mutex);
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this->send_pkt(SPI_DIV, SPI_DIVIDER, POKE32_CMD);
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this->wait_for_ack(_seq_out-_window_size);
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_ctrl_word_cache = 0; // force update first time around
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}
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boost::uint32_t transact_spi(
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int which_slave,
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const spi_config_t &config,
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boost::uint32_t data,
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size_t num_bits,
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bool readback
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){
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boost::mutex::scoped_lock lock(_mutex);
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//load control word
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boost::uint32_t ctrl_word = 0;
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ctrl_word |= ((which_slave & 0xffffff) << 0);
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ctrl_word |= ((num_bits & 0x3ff) << 24);
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if (config.mosi_edge == spi_config_t::EDGE_FALL) ctrl_word |= (1 << 31);
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if (config.miso_edge == spi_config_t::EDGE_RISE) ctrl_word |= (1 << 30);
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//load data word (must be in upper bits)
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const boost::uint32_t data_out = data << (32 - num_bits);
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//conditionally send control word
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if (_ctrl_word_cache != ctrl_word){
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this->send_pkt(SPI_CTRL, ctrl_word, POKE32_CMD);
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this->wait_for_ack(_seq_out-_window_size);
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_ctrl_word_cache = ctrl_word;
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}
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//send data word
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this->send_pkt(SPI_DATA, data_out, POKE32_CMD);
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this->wait_for_ack(_seq_out-_window_size);
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//conditional readback
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if (readback){
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this->send_pkt(U2_REG_SPI_RB, 0, PEEK32_CMD);
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return this->wait_for_ack(_seq_out);
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}
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return 0;
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}
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/*******************************************************************
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* Update methods for time
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******************************************************************/
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void set_time(const uhd::time_spec_t &time){
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boost::mutex::scoped_lock lock(_mutex);
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_time = time;
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_use_time = _time != uhd::time_spec_t(0.0);
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if (_use_time) _timeout = MASSIVE_TIMEOUT; //permanently sets larger timeout
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_start_of_burst = true;
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}
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void set_tick_rate(const double rate){
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boost::mutex::scoped_lock lock(_mutex);
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_tick_rate = rate;
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}
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void set_late_policy(const bool skip_late)
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{
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_skip_late = skip_late;
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}
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private:
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/*******************************************************************
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* Primary control and interaction private methods
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******************************************************************/
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UHD_INLINE void send_pkt(wb_addr_type addr, boost::uint32_t data, int cmd){
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managed_send_buffer::sptr buff = _xport->get_send_buff(0.0);
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if (not buff){
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throw uhd::runtime_error("fifo ctrl timed out getting a send buffer");
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}
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boost::uint32_t *trans = buff->cast<boost::uint32_t *>();
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trans[0] = htonl(++_seq_out);
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boost::uint32_t *pkt = trans + 1;
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//load packet info
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vrt::if_packet_info_t packet_info;
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packet_info.packet_type = vrt::if_packet_info_t::PACKET_TYPE_CONTEXT;
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packet_info.num_payload_words32 = 2;
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packet_info.num_payload_bytes = packet_info.num_payload_words32*sizeof(boost::uint32_t);
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packet_info.packet_count = _seq_out;
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packet_info.sid = _sid;
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packet_info.tsf = _time.to_ticks(_tick_rate);
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packet_info.sob = _start_of_burst;
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_start_of_burst = false; //only set once by set time, then cleared
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packet_info.eob = false;
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packet_info.has_sid = true;
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packet_info.has_cid = false;
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packet_info.has_tsi = false;
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packet_info.has_tsf = _use_time;
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packet_info.has_tlr = false;
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//load header
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vrt::if_hdr_pack_be(pkt, packet_info);
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//time command flags
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if (_skip_late) cmd |= SKIP_LATE_CMD;
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if (_use_time) cmd |= TIME_WAIT_CMD;
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//load payload
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const boost::uint32_t ctrl_word = (addr & 0xff) | cmd | (_seq_out << 16);
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pkt[packet_info.num_header_words32+0] = htonl(ctrl_word);
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pkt[packet_info.num_header_words32+1] = htonl(data);
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//send the buffer over the interface
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buff->commit(sizeof(boost::uint32_t)*(packet_info.num_packet_words32+1));
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}
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UHD_INLINE bool wraparound_lt16(const boost::int16_t i0, const boost::int16_t i1){
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if (((i0 ^ i1) & 0x8000) == 0) //same sign bits
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return boost::uint16_t(i0) < boost::uint16_t(i1);
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return boost::int16_t(i1 - i0) > 0;
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}
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UHD_INLINE boost::uint32_t wait_for_ack(const boost::uint16_t seq_to_ack){
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while (wraparound_lt16(_seq_ack, seq_to_ack)){
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managed_recv_buffer::sptr buff = _xport->get_recv_buff(_timeout);
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if (not buff){
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throw uhd::runtime_error("fifo ctrl timed out looking for acks");
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}
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const boost::uint32_t *pkt = buff->cast<const boost::uint32_t *>();
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vrt::if_packet_info_t packet_info;
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packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
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vrt::if_hdr_unpack_be(pkt, packet_info);
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//extract the payloads
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const boost::int32_t header = ntohl(pkt[packet_info.num_header_words32+0]);
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const boost::int32_t rb_data = ntohl(pkt[packet_info.num_header_words32+1]);
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const boost::int32_t last_header = ntohl(pkt[packet_info.num_header_words32+2]);
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const boost::int32_t fifo_occupied = ntohl(pkt[packet_info.num_header_words32+3]);
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const boost::uint16_t this_seq = header >> 16;
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const boost::uint16_t last_seq = last_header >> 16;
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const boost::uint16_t result_fifo_occupied = fifo_occupied >> 16;
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const boost::uint16_t command_fifo_occupied = fifo_occupied & 0xffff;
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//check if we lost packets from device -> host
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const boost::uint16_t next_recv_seq = _prev_recv_seq+1;
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if (next_recv_seq != this_seq)
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{
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UHD_MSG(error) << boost::format(
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"Detected packet loss from device to host:\n"
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"Host expected sequence 0x%x, but got 0x%x"
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) % next_recv_seq % this_seq << std::endl;
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}
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//check if we lost packets from host -> device
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if (_total_recv_packets != 0 and _prev_recv_seq != last_seq)
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{
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UHD_MSG(error) << boost::format(
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"Detected packet loss from host to device:\n"
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"Device expected last sequence 0x%x, but saw 0x%x"
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) % _prev_recv_seq % last_seq << std::endl;
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}
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if (result_fifo_occupied > FIFO_DEPTH/2 or command_fifo_occupied > FIFO_DEPTH/2)
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{
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UHD_MSG(warning) << boost::format(
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"FIFOs are past half capacity!\n"
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"Command FIFO occupancy: %d/%d\n"
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"Result FIFO occupancy: %d/%d"
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) % command_fifo_occupied % FIFO_DEPTH % result_fifo_occupied % FIFO_DEPTH << std::endl;
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}
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//store state for next recv iteration
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_total_recv_packets++;
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_prev_recv_seq = this_seq;
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_seq_ack = this_seq;
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if (_seq_ack == seq_to_ack) return rb_data;
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}
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return 0;
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}
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zero_copy_if::sptr _xport;
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const boost::uint32_t _sid;
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const boost::uint32_t _window_size;
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boost::mutex _mutex;
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boost::uint16_t _seq_out;
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boost::uint16_t _seq_ack;
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boost::uint16_t _prev_recv_seq;
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boost::uint16_t _next_recv_seq;
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boost::uint64_t _total_recv_packets;
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uhd::time_spec_t _time;
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bool _start_of_burst;
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bool _skip_late;
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bool _use_time;
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double _tick_rate;
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double _timeout;
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boost::uint32_t _ctrl_word_cache;
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};
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umtrx_fifo_ctrl::sptr umtrx_fifo_ctrl::make(zero_copy_if::sptr xport, const boost::uint32_t sid, const size_t window_size){
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return sptr(new umtrx_fifo_ctrl_impl(xport, sid, boost::uint32_t(window_size)));
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}
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