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https://github.com/fairwaves/UHD-Fairwaves.git
synced 2025-10-22 23:31:59 +00:00
fpga: bump compat minor, work on late flag
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@@ -247,22 +247,24 @@ module settings_fifo_ctrl
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always @(posedge clock)
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vita_time_reg <= vita_time;
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wire late;
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wire late, now;
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`ifndef FIFO_CTRL_NO_TIME
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time_compare time_compare(
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.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
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.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late), .now(now));
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`else
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assign late = 1;
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assign now = 1;
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`endif
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//these config flags are available only in the LOAD_CMD state (where we wait)
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wire time_wait = out_command_hdr[9];
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wire skip_late = out_command_hdr[10]; //TODO (implement)
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reg cmd_was_late;
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//action occurs in the event state and when there is fifo space (should always be true)
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//the third condition is that all peripherals in the perfs signal are ready/active high
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//the fourth condition is that is an event time has been set, action is delayed until that time
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wire time_ready = (time_wait)? late : 1;
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wire time_ready = (time_wait)? (late || now) : 1;
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wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
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assign command_fifo_read = action;
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@@ -282,6 +284,7 @@ module settings_fifo_ctrl
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command_ticks_reg <= out_command_ticks;
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command_hdr_reg <= out_command_hdr;
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command_data_reg <= out_command_data;
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cmd_was_late <= late; //TODO do something with
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end
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EVENT_CMD: begin // poking and peeking happens here!
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@@ -448,7 +448,7 @@ module umtrx_core
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// Buffer Pool Status -- Slave #5
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//compatibility number -> increment when the fpga has been sufficiently altered
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localparam compat_num = {16'd9, 16'd1}; //major, minor
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localparam compat_num = {16'd9, 16'd2}; //major, minor
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wire [31:0] irq_readback = {16'b0, aux_ld2, aux_ld1, button, spi_ready, 12'b0};
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@@ -57,6 +57,10 @@ public:
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_seq_ack(0),
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_prev_recv_seq(0),
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_total_recv_packets(0),
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_start_of_burst(false),
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_skip_late(false),
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_use_time(false),
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_tick_rate(1.0),
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_timeout(ACK_TIMEOUT)
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{
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UHD_MSG(status) << "fifo_ctrl.window_size = " << _window_size << std::endl;
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@@ -162,6 +166,7 @@ public:
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_time = time;
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_use_time = _time != uhd::time_spec_t(0.0);
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if (_use_time) _timeout = MASSIVE_TIMEOUT; //permanently sets larger timeout
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_start_of_burst = true;
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}
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void set_tick_rate(const double rate){
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@@ -169,6 +174,11 @@ public:
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_tick_rate = rate;
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}
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void set_late_policy(const bool skip_late)
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{
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_skip_late = skip_late;
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}
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private:
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/*******************************************************************
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@@ -191,7 +201,8 @@ private:
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packet_info.packet_count = _seq_out;
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packet_info.sid = _sid;
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packet_info.tsf = _time.to_ticks(_tick_rate);
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packet_info.sob = false;
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packet_info.sob = _start_of_burst;
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_start_of_burst = false; //only set once by set time, then cleared
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packet_info.eob = false;
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packet_info.has_sid = true;
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packet_info.has_cid = false;
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@@ -202,8 +213,11 @@ private:
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//load header
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vrt::if_hdr_pack_be(pkt, packet_info);
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//load payload
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//time command flags
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if (_skip_late) cmd |= SKIP_LATE_CMD;
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if (_use_time) cmd |= TIME_WAIT_CMD;
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//load payload
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const boost::uint32_t ctrl_word = (addr & 0xff) | cmd | (_seq_out << 16);
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pkt[packet_info.num_header_words32+0] = htonl(ctrl_word);
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pkt[packet_info.num_header_words32+1] = htonl(data);
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@@ -288,6 +302,8 @@ private:
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boost::uint16_t _next_recv_seq;
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boost::uint64_t _total_recv_packets;
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uhd::time_spec_t _time;
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bool _start_of_burst;
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bool _skip_late;
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bool _use_time;
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double _tick_rate;
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double _timeout;
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