fpga: bump compat minor, work on late flag

This commit is contained in:
Josh Blum
2015-07-22 20:05:19 -07:00
parent 63e2ee1967
commit 7b1348ee97
3 changed files with 25 additions and 6 deletions

View File

@@ -247,22 +247,24 @@ module settings_fifo_ctrl
always @(posedge clock)
vita_time_reg <= vita_time;
wire late;
wire late, now;
`ifndef FIFO_CTRL_NO_TIME
time_compare time_compare(
.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late), .now(now));
`else
assign late = 1;
assign now = 1;
`endif
//these config flags are available only in the LOAD_CMD state (where we wait)
wire time_wait = out_command_hdr[9];
wire skip_late = out_command_hdr[10]; //TODO (implement)
reg cmd_was_late;
//action occurs in the event state and when there is fifo space (should always be true)
//the third condition is that all peripherals in the perfs signal are ready/active high
//the fourth condition is that is an event time has been set, action is delayed until that time
wire time_ready = (time_wait)? late : 1;
wire time_ready = (time_wait)? (late || now) : 1;
wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
assign command_fifo_read = action;
@@ -282,6 +284,7 @@ module settings_fifo_ctrl
command_ticks_reg <= out_command_ticks;
command_hdr_reg <= out_command_hdr;
command_data_reg <= out_command_data;
cmd_was_late <= late; //TODO do something with
end
EVENT_CMD: begin // poking and peeking happens here!

View File

@@ -448,7 +448,7 @@ module umtrx_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
localparam compat_num = {16'd9, 16'd1}; //major, minor
localparam compat_num = {16'd9, 16'd2}; //major, minor
wire [31:0] irq_readback = {16'b0, aux_ld2, aux_ld1, button, spi_ready, 12'b0};

View File

@@ -57,6 +57,10 @@ public:
_seq_ack(0),
_prev_recv_seq(0),
_total_recv_packets(0),
_start_of_burst(false),
_skip_late(false),
_use_time(false),
_tick_rate(1.0),
_timeout(ACK_TIMEOUT)
{
UHD_MSG(status) << "fifo_ctrl.window_size = " << _window_size << std::endl;
@@ -162,6 +166,7 @@ public:
_time = time;
_use_time = _time != uhd::time_spec_t(0.0);
if (_use_time) _timeout = MASSIVE_TIMEOUT; //permanently sets larger timeout
_start_of_burst = true;
}
void set_tick_rate(const double rate){
@@ -169,6 +174,11 @@ public:
_tick_rate = rate;
}
void set_late_policy(const bool skip_late)
{
_skip_late = skip_late;
}
private:
/*******************************************************************
@@ -191,7 +201,8 @@ private:
packet_info.packet_count = _seq_out;
packet_info.sid = _sid;
packet_info.tsf = _time.to_ticks(_tick_rate);
packet_info.sob = false;
packet_info.sob = _start_of_burst;
_start_of_burst = false; //only set once by set time, then cleared
packet_info.eob = false;
packet_info.has_sid = true;
packet_info.has_cid = false;
@@ -202,8 +213,11 @@ private:
//load header
vrt::if_hdr_pack_be(pkt, packet_info);
//load payload
//time command flags
if (_skip_late) cmd |= SKIP_LATE_CMD;
if (_use_time) cmd |= TIME_WAIT_CMD;
//load payload
const boost::uint32_t ctrl_word = (addr & 0xff) | cmd | (_seq_out << 16);
pkt[packet_info.num_header_words32+0] = htonl(ctrl_word);
pkt[packet_info.num_header_words32+1] = htonl(data);
@@ -288,6 +302,8 @@ private:
boost::uint16_t _next_recv_seq;
boost::uint64_t _total_recv_packets;
uhd::time_spec_t _time;
bool _start_of_burst;
bool _skip_late;
bool _use_time;
double _tick_rate;
double _timeout;