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102 lines
2.4 KiB
Verilog
102 lines
2.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// AD9510 Register Map (from datasheet Rev. A)
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/* INSTRUCTION word format (16 bits)
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* 15 Read = 1, Write = 0
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* 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
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* 12:0 Address
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*/
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/* ADDR Contents Value (hex)
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* 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate
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* 04 A Counter
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* 05-06 B Counter
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* 07-0A PLL Control
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* 0B-0C R Divider
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* 0D PLL Control
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* 34-3A Fine Delay
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* 3C-3F LVPECL Outs
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* 40-43 LVDS/CMOS Outs
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* 45 Clock select, power down
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* 48-57 Dividers
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* 58 Func and Sync
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* 5A Update regs
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*/
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module spi
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(input reset,
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input clk,
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// SPI signals
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output sen,
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output sclk,
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input sdi,
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output sdo,
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// Interfaces
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input read_1,
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input write_1,
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input [15:0] command_1,
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input [15:0] wdata_1,
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output [15:0] rdata_1,
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output reg done_1,
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input msb_first_1,
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input [5:0] command_width_1,
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input [5:0] data_width_1,
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input [7:0] clkdiv_1
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);
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reg [15:0] command, wdata, rdata;
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reg done;
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always @(posedge clk)
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if(reset)
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done_1 <= #1 1'b0;
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always @(posedge clk)
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if(reset)
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begin
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counter <= #1 7'd0;
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command <= #1 20'd0;
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end
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else if(start)
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begin
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counter <= #1 7'd1;
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command <= #1 {read,w,addr_data};
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end
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else if( |counter && ~done )
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begin
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counter <= #1 counter + 7'd1;
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if(~counter[0])
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command <= {command[22:0],1'b0};
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end
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wire done = (counter == 8'd49);
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assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything
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assign sclk = ~counter[0];
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assign sdo = command[23];
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endmodule // clock_control
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