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29 lines
977 B
Verilog
29 lines
977 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module add2
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#(parameter WIDTH=16)
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(input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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output [WIDTH-1:0] sum);
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wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
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assign sum = sum_int[WIDTH:1]; // Note -- will have some bias
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endmodule // add2
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