mirror of
https://github.com/fairwaves/UHD-Fairwaves.git
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99 lines
3.5 KiB
Verilog
99 lines
3.5 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//The following module effects the IO of the DDC chain.
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//By default, this entire module is a simple pass-through.
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module dsp_rx_glue
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#(
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//the dsp unit number: 0, 1, 2...
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parameter DSPNO = 0,
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//frontend bus width
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parameter WIDTH = 24
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)
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(
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//control signals
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input clock, input reset, input clear, input enable,
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//user settings bus, controlled through user setting regs API
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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//full rate inputs directly from the RX frontend
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input [WIDTH-1:0] frontend_i,
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input [WIDTH-1:0] frontend_q,
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//full rate outputs directly to the DDC chain
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output [WIDTH-1:0] ddc_in_i,
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output [WIDTH-1:0] ddc_in_q,
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//strobed samples {I16,Q16} from the RX DDC chain
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input [31:0] ddc_out_sample,
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input ddc_out_strobe, //high on valid sample
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output ddc_out_enable, //enables DDC module
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//strobbed baseband samples {I16,Q16} from this module
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output [31:0] bb_sample,
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output bb_strobe, //high on valid sample
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//debug output (optional)
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output [31:0] debug
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);
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generate
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if (DSPNO==0) begin
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`ifndef RX_DSP0_MODULE
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assign ddc_in_i = frontend_i;
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assign ddc_in_q = frontend_q;
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assign bb_sample = ddc_out_sample;
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assign bb_strobe = ddc_out_strobe;
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assign ddc_out_enable = enable;
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`else
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`RX_DSP0_MODULE #(.WIDTH(WIDTH)) rx_dsp0_custom
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(
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.clock(clock), .reset(reset), .clear(clear), .enable(enable),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.frontend_i(frontend_i), .frontend_q(frontend_q),
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.ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
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.ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
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.bb_sample(bb_sample), .bb_strobe(bb_strobe)
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);
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`endif
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end
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else begin
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`ifndef RX_DSP1_MODULE
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assign ddc_in_i = frontend_i;
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assign ddc_in_q = frontend_q;
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assign bb_sample = ddc_out_sample;
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assign bb_strobe = ddc_out_strobe;
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assign ddc_out_enable = enable;
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`else
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`RX_DSP1_MODULE #(.WIDTH(WIDTH)) rx_dsp1_custom
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(
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.clock(clock), .reset(reset), .clear(clear), .enable(enable),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.frontend_i(frontend_i), .frontend_q(frontend_q),
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.ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
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.ddc_out_sample(ddc_out_sample), .ddc_out_strobe(ddc_out_strobe), .ddc_out_enable(ddc_out_enable),
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.bb_sample(bb_sample), .bb_strobe(bb_strobe)
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);
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`endif
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end
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endgenerate
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endmodule //dsp_rx_glue
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