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78 lines
1.9 KiB
Verilog
78 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module simple_timer
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#(parameter BASE=0)
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(input clk, input reset,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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output reg onetime_int, output reg periodic_int);
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reg [31:0] onetime_ctr;
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always @(posedge clk)
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if(reset)
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begin
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onetime_int <= 0;
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onetime_ctr <= 0;
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end
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else
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if(set_stb & (set_addr == BASE))
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begin
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onetime_int <= 0;
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onetime_ctr <= set_data;
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end
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else
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begin
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if(onetime_ctr == 1)
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onetime_int <= 1;
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if(onetime_ctr != 0)
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onetime_ctr <= onetime_ctr - 1;
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else
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onetime_int <= 0;
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end // else: !if(set_stb & (set_addr == BASE))
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reg [31:0] periodic_ctr, period;
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always @(posedge clk)
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if(reset)
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begin
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periodic_int <= 0;
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periodic_ctr <= 0;
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period <= 0;
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end
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else
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if(set_stb & (set_addr == (BASE+1)))
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begin
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periodic_int <= 0;
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periodic_ctr <= set_data;
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period <= set_data;
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end
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else
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if(periodic_ctr == 1)
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begin
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periodic_int <= 1;
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periodic_ctr <= period;
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end
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else
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if(periodic_ctr != 0)
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begin
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periodic_int <= 0;
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periodic_ctr <= periodic_ctr - 1;
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end
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endmodule // simple_timer
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