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58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module timer
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(input wb_clk_i, input rst_i,
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input cyc_i, input stb_i, input [2:0] adr_i,
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input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
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input sys_clk_i, input [31:0] master_time_i,
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output int_o );
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reg [31:0] time_wb;
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always @(posedge wb_clk_i)
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time_wb <= master_time_i;
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assign ack_o = stb_i;
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reg [31:0] int_time;
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reg int_reg;
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always @(posedge sys_clk_i)
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if(rst_i)
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begin
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int_time <= 0;
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int_reg <= 0;
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end
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else if(|int_time && (master_time_i == int_time))
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begin
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int_time <= 0;
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int_reg <= 1;
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end
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else if(stb_i & we_i)
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begin
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int_time <= dat_i;
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int_reg <= 0;
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end
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assign dat_o = time_wb;
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assign int_o = int_reg;
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endmodule // timer
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