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paulmataruso:master paulmataruso:fpga_wip paulmataruso:idle_reset paulmataruso:sergforce/zpu_fix paulmataruso:achemeris/debug-spi-issue paulmataruso:fifo_ctrl_work paulmataruso:fairwaves/4xDDC paulmataruso:LTE_30_72MHz_update paulmataruso:fairwaves/LTE_30_72MHz
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paulmataruso:master paulmataruso:fpga_wip paulmataruso:idle_reset paulmataruso:sergforce/zpu_fix paulmataruso:achemeris/debug-spi-issue paulmataruso:fifo_ctrl_work paulmataruso:fairwaves/4xDDC paulmataruso:LTE_30_72MHz_update paulmataruso:fairwaves/LTE_30_72MHz
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3 Commits
fpga_wip ... fifo_ctrl_

Author SHA1 Message Date
Josh Blum
7b1348ee97 fpga: bump compat minor, work on late flag 2015-07-22 20:05:19 -07:00
Josh Blum
63e2ee1967 fpga: implement fifo control tracking info 
* detect loss host to device, and device to host
* warn on near fifo capacity
* added time wait flag (replaces tsf for waiting)
* added skip late flag (implementation TODO)
 2015-07-22 18:14:04 -07:00
Josh Blum
89394c9a58 fpga: larger long fifo with 64 entries 2015-07-22 13:01:10 -07:00
65 changed files with 941 additions and 3811 deletions
Expand all files Collapse all files

2
README
View File

@@ -120,5 +120,5 @@ then RX VITA time alignment will not be possible due to ambiguity.
Currently, the adc sample strobes are driven from a common sigal.
simple_gemac_wrapper.v was modified to have an axi_packet_gate in the eth transmit direction.
This guarantees thats a packet is 100% buffered before being sent out over ethernet.
This guarantees thats a packet is 100% buffered before being send out over ethernet.
This avoid in-packet underflow when the mac is fed from a slower clock domain.

94
debian/changelog vendored
View File

@@ -1,97 +1,3 @@
umtrx (1.0.13) trusty; urgency=low
* [ZPU/host] Read TCXO DAC calibration from EEPROM once on UmTRX boot instead
of reading and setting it every time we launch a UHD app.
* [ZPU] Faster GPSDO converging when setting TCXO DAC value manually.
* [ZPU] BUGFIX: Optimize ZPU image size to avoid stack overflow.
* [ZPU] Print and check available ZPU stack space when compiling images.
* [FPGA/ZPU] Increase FPGA minor version number, generate new stable images.
-- Alexander Chemeris <Alexander.Chemeris@fairwaves.co> Fri, 04 Aug 2017 15:55:56 +0300
umtrx (1.0.12) trusty; urgency=low
* [ZPU] BUGFIX: Fix GPSDO rounding issue to stabilize frequency down to +-1 Hz @ 52MHz.
* [ZPU] Export measured frequency and last PPS time over the control socket.
* [ZPU] Allow GPSDO debug enable/disable over the control socket.
* [ZPU] Print firmware minor version and git hash on startup.
* [ZPU] Make debug output on wrong packets less scary for users.
* [host] Cleanup UmTRX detection on UHD startup.
* [host] Export DC calibration registers through the property tree.
* [host] Fix build with newer UHD versions.
* [utils] BUGIX: Multiple fixes for the umtrx_ty_tree.py module.
* [utils] Lowercase sensor names in umtrx2collectd.
-- Alexander Chemeris <Alexander.Chemeris@fairwaves.co> Thu, 27 Jul 2017 23:46:07 +0300
umtrx (1.0.11) trusty; urgency=low
* collectd: use 'fairwaves-monitoring' user to run plugin
-- Kirill Zakharenko <earwin@gmail.com> Sun, 27 Mar 2016 19:37:39 +0100
umtrx (1.0.10) trusty; urgency=low
* collectd: rewritten counter collection plugin
-- Kirill Zakharenko <earwin@gmail.com> Mon, 21 Mar 2016 19:21:00 +0100
umtrx (1.0.9) trusty; urgency=low
* collectd: osmo-nitb counter collection plugin
-- Kirill Zakharenko <earwin@gmail.com> Mon, 24 Feb 2016 19:35:56 +0300
umtrx (1.0.8) trusty; urgency=low
* host: integrate support class for umsel2
* host: integrate support class for umsel2
* host: implement selection for umsel2 + lms
* host: umsel2 register work for adf355-2
* host: umsel2 adf355-2 tuning algorithm
* host: freq update sequence, copied registers from gui
* host: print locked for debugging
* umsel: device args for enabling umsel2 and verbose
* add lmsvga1 device args parameter to override VGA1_DEF
* autodetect DCDC translation version on startup
* add lmsvga2 args parameter to override UMTRX_VGA2_DEF
* turn off vin bypass to amplifiers by default
* throw exception if incorrect DCDC version were provided
-- Kirill Zakharenko <earwin@gmail.com> Mon, 28 Dec 2015 15:07:56 +0300
umtrx (1.0.7) trusty; urgency=low
* host: Properly handle most corner cases in VSWR calculations
* host: Add "STRING" to umtrx_monitor error output
* host: Add string getters/setters to the Python property tree library
* host: Checking in umtrx_query_versions.py
* debian: packaged python utils in host/utils
-- Kirill Zakharenko <earwin@gmail.com> Mon, 25 Dec 2015 19:35:56 +0100
umtrx (1.0.6) trusty; urgency=low
* host: make boost property tree thread safe
* host: support string type in JSON query
* debian: build now produces an additional package with debug symbols
* umtrx_firmware: fixed typo preventing it from working
-- Kirill Zakharenko <earwin@gmail.com> Mon, 21 Dec 2015 14:23:56 +0300
umtrx (1.0.5) trusty; urgency=low
* host: disable umtrx_fifo_ctrl cache of spi config
* host: Fix getters in umtrx_property_tree.py.
* debian: added firmware to package and umtrx_firmware script to handle it
* fpga: created axi stream controled spi core
* fpga: use axi stream spi core (still single dest)
* fpga: connect both spi settings drivers
* fpga: simplify spi setting regs with generate loop
* fpga: updated 4x ddc image for spi work
-- Kirill Zakharenko <earwin@gmail.com> Mon, 23 Nov 2015 15:51:56 +0300
umtrx (1.0.4) unstable; urgency=low
* Do not add 'g' to a git id when creating a version string.

11
debian/control vendored
View File

@@ -17,8 +17,6 @@ Section: libs
Architecture: any
Pre-Depends: multiarch-support, ${misc:Pre-Depends}
Depends: ${shlibs:Depends}, ${misc:Depends}, uhd-umtrx
Conflicts: umtrx-uhd
Replaces: umtrx-uhd
Recommends: python
Description: Fairwaves UmTRX driver - runtime utilities
The industrial grade dual-channel wide-band SDR transceiver.
@@ -27,14 +25,5 @@ Package: uhd-umtrx
Section: libs
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}
Conflicts: umtrx-uhd
Replaces: umtrx-uhd
Description: Fairwaves UmTRX driver - UHD plugin module
The industrial grade dual-channel wide-band SDR transceiver.
Package: umtrx-dbg
Section: debug
Architecture: any
Depends: umtrx, uhd-umtrx, ${misc:Depends}
Description: Fairwaves UmTRX driver - debug symbols
The industrial grade dual-channel wide-band SDR transceiver.

3
debian/rules vendored
View File

@@ -16,6 +16,3 @@ export DH_OPTIONS
override_dh_auto_configure:
dh_auto_configure -- -DLIB_SUFFIX="/$(DEB_HOST_MULTIARCH)"
override_dh_strip:
dh_strip --dbg-package=umtrx-dbg

7
debian/umtrx.install vendored
View File

@@ -1,8 +1 @@
usr/bin
images/u2plus_umtrx_v2.bin images/umtrx_txrx_uhd.bin usr/share/umtrx/firmware
host/utils/umtrx_property_tree.py host/utils/umtrx_vswr.py usr/share/umtrx
host/utils/umtrx_query_sensors.py host/utils/umtrx_query_versions.py host/utils/umtrx_net_burner.py usr/share/umtrx
host/utils/collectd/umtrx.types.db usr/share/collectd
host/utils/collectd/umtrx2collectd.py usr/share/umtrx
host/utils/collectd/umtrx.conf etc/collectd/collectd.conf.d

3
debian/umtrx.links vendored
View File

@@ -1,3 +0,0 @@
/usr/share/umtrx/umtrx_net_burner.py /usr/bin/umtrx_net_burner
/usr/share/umtrx/umtrx_query_sensors.py /usr/bin/umtrx_query_sensors
/usr/share/umtrx/umtrx_query_versions.py /usr/bin/umtrx_query_versions

1
fpga/control_lib/Makefile.srcs
View File

@@ -58,6 +58,5 @@ gpio_atr.v \
user_settings.v \
settings_fifo_ctrl.v \
simple_spi_core.v \
axis_spi_core.v \
simple_i2c_core.v \
))

243
fpga/control_lib/axis_spi_core.v
View File

@@ -1,243 +0,0 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Simple SPI core, the simplest, yet complete spi core I can think of
// Settings register controlled.
// 2 settings regs, control and data
// 1 32-bit readback and status signal
// Settings reg map:
//
// BASE+0 divider setting
// bits [15:0] spi clock divider
//
// BASE+1 configuration input
// bits [23:0] slave select, bit0 = slave0 enabled
// bits [29:24] num bits (1 through 32)
// bit [30] data input edge = in data bit latched on rising edge of clock
// bit [31] data output edge = out data bit latched on rising edge of clock
//
// BASE+2 input data
// Writing this register begins a spi transaction.
// Bits are latched out from bit 0.
// Therefore, load this register in reverse.
//
// Readback
// Bits are latched into bit 0.
// Therefore, data will be in-order.
module axis_spi_core
#(
//set to 1 for ILA
parameter DEBUG = 0,
//tdest width for number of core users
parameter DESTW = 1,
//width of serial enables (up to 24 is possible)
parameter WIDTH = 8,
//idle state of the spi clock
parameter CLK_IDLE = 0,
//idle state of the serial enables
parameter SEN_IDLE = 24'hffffff
)
(
//clock and synchronous reset
input clock, input reset,
//configuration settings bus
input [DESTW-1:0] CONFIG_tdest,
input [79:0] CONFIG_tdata,
input CONFIG_tvalid,
output CONFIG_tready,
//32-bit data readback
output reg [DESTW-1:0] READBACK_tdest,
output [31:0] READBACK_tdata,
output READBACK_tvalid,
input READBACK_tready,
//spi interface, slave selects, clock, data in, data out
output [WIDTH-1:0] sen,
output sclk,
output mosi,
input miso
);
//state
localparam WAIT_CONFIG = 0;
localparam PRE_IDLE = 1;
localparam CLK_REG = 2;
localparam CLK_INV = 3;
localparam POST_IDLE = 4;
localparam IDLE_SEN = 5;
localparam WAIT_READBACK = 6;
reg [2:0] state;
//configuration settings
reg [15:0] sclk_divider;
reg [23:0] slave_select;
reg [5:0] num_bits;
reg datain_edge, dataout_edge;
//output ready/valid signals
assign CONFIG_tready = (state == WAIT_CONFIG);
assign READBACK_tvalid = (state == WAIT_READBACK);
//serial clock either idles or is in one of two clock states
reg sclk_reg;
assign sclk = sclk_reg;
//serial enables either idle or enabled based on state
wire sen_is_idle = (state == WAIT_CONFIG) || (state == IDLE_SEN);
wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
reg [WIDTH-1:0] sen_reg;
always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
assign sen = sen_reg;
//data output shift register
reg [31:0] dataout_reg;
wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
assign mosi = dataout_reg[31];
//data input shift register
reg [31:0] datain_reg;
wire [31:0] datain_next = {datain_reg[30:0], miso};
assign READBACK_tdata = datain_reg;
//counter for spi clock
reg [15:0] sclk_counter;
wire sclk_counter_done = (sclk_counter == sclk_divider);
wire [15:0] sclk_counter_next = (sclk_counter_done)? 0 : sclk_counter + 1;
//counter for latching bits miso/mosi
reg [6:0] bit_counter;
wire [6:0] bit_counter_next = bit_counter + 1;
wire bit_counter_done = (bit_counter_next == num_bits);
always @(posedge clock) begin
if (reset) begin
state <= WAIT_CONFIG;
sclk_reg <= CLK_IDLE;
end
else begin
case (state)
WAIT_CONFIG: begin
if (CONFIG_tvalid && CONFIG_tready) begin
state <= PRE_IDLE;
end
{sclk_divider, dataout_edge, datain_edge, num_bits, slave_select, dataout_reg} <= CONFIG_tdata;
READBACK_tdest <= CONFIG_tdest;
sclk_counter <= 0;
bit_counter <= 0;
sclk_reg <= CLK_IDLE;
end
PRE_IDLE: begin
if (sclk_counter_done) state <= CLK_REG;
sclk_counter <= sclk_counter_next;
sclk_reg <= CLK_IDLE;
end
CLK_REG: begin
if (sclk_counter_done) begin
state <= CLK_INV;
if (datain_edge != CLK_IDLE) datain_reg <= datain_next;
if (dataout_edge != CLK_IDLE && bit_counter != 0) dataout_reg <= dataout_next;
sclk_reg <= ~CLK_IDLE; //transition to rising when CLK_IDLE == 0
end
sclk_counter <= sclk_counter_next;
end
CLK_INV: begin
if (sclk_counter_done) begin
state <= (bit_counter_done)? POST_IDLE : CLK_REG;
bit_counter <= bit_counter_next;
if (datain_edge == CLK_IDLE) datain_reg <= datain_next;
if (dataout_edge == CLK_IDLE && ~bit_counter_done) dataout_reg <= dataout_next;
sclk_reg <= CLK_IDLE; //transition to falling when CLK_IDLE == 0
end
sclk_counter <= sclk_counter_next;
end
POST_IDLE: begin
if (sclk_counter_done) state <= IDLE_SEN;
sclk_counter <= sclk_counter_next;
sclk_reg <= CLK_IDLE;
end
IDLE_SEN: begin
if (sclk_counter_done) state <= WAIT_READBACK;
sclk_counter <= sclk_counter_next;
sclk_reg <= CLK_IDLE;
end
WAIT_READBACK: begin
if (READBACK_tready && READBACK_tvalid) begin
state <= WAIT_CONFIG;
end
end
default: state <= WAIT_CONFIG;
endcase //state
end
end
/*******************************************************************
* Debug
******************************************************************/
generate
if (DEBUG == 1) begin
wire [35:0] CONTROL0;
chipscope_icon chipscope_icon
(
.CONTROL0(CONTROL0)
);
wire [255:0] DATA;
wire [7:0] TRIG0;
chipscope_ila chipscope_ila
(
.CONTROL(CONTROL0),
.CLK(clock),
.DATA(DATA),
.TRIG0(TRIG0)
);
assign TRIG0 =
{
4'b0,
CONFIG_tvalid, CONFIG_tready,
READBACK_tvalid, READBACK_tready
};
assign DATA[79:0] = CONFIG_tdata;
assign DATA[111:80] = READBACK_tdata;
assign DATA[112] = CONFIG_tvalid;
assign DATA[113] = CONFIG_tready;
assign DATA[114] = READBACK_tvalid;
assign DATA[115] = READBACK_tready;
assign DATA[127:120] = state;
end
endgenerate
endmodule //axis_spi_core

50
fpga/control_lib/s6_icap_wb.v
View File

@@ -21,52 +21,50 @@
module s6_icap_wb
(input clk, input clk_icap, input reset,
input cyc_i, input stb_i, input we_i, output reg ack_o,
input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out);
input [31:0] dat_i, output reg[31:0] dat_o);//, output [31:0] debug_out);
// reg slow_clk_icap;
// always @(posedge clk_icap) slow_clk_icap <= ~slow_clk_icap;
reg slow_clk_icap;
always @(posedge clk_icap) slow_clk_icap <= ~slow_clk_icap;
wire BUSY, CE, WRITE;
wire[15:0] s1_dat_i;
// reg[31:0] s_dat_o;
// wire[31:0] s1_dat_o;
wire[31:0] s1_dat_i;
reg[31:0] s_dat_o;
wire[31:0] s1_dat_o;
// assign s1_dat_o[31:16] = 16'd0;
assign dat_o = 0;
assign s1_dat_o[31:16] = 16'd0;
wire full, empty;
fifo_xlnx_32x36_2clk icap_fifo
fifo_xlnx_16x40_2clk icap_fifo
(.rst(reset),
.wr_clk(clk), .din(dat_i[15:0]), .wr_en(we_i & cyc_i & stb_i & ~ack_o & ~full), .full(full),
.rd_clk(clk_icap), .dout(s1_dat_i), .rd_en(~empty), .empty(empty));
.wr_clk(clk), .din(dat_i), .wr_en(we_i & stb_i & ~ack_o & ~full), .full(full),
.rd_clk(slow_clk_icap), .dout(s1_dat_i), .rd_en(~empty), .empty(empty));
// assign WRITE = empty;
assign WRITE = empty;
assign CE = empty;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst
(.BUSY(), // Busy output, active high
.O(), // 16-bit data output
.CE(CE), // Clock enable input, active low
.CLK(clk_icap), // Clock input
.I(s1_dat_i), // 16-bit data input
.WRITE(1'b0) // Write input, 0 - WRITE, 1 - READ
(.BUSY(BUSY), // Busy output
.O(s1_dat_o[15:0]), // 16-bit data output
.CE(CE), // Clock enable input
.CLK(slow_clk_icap), // Clock input
.I(s1_dat_i[15:0]), // 16-bit data input
.WRITE(WRITE) // Write input
);
//cross back to Wishbone clock domain
always @(posedge clk)
if (reset)
begin
//s_dat_o <= 32'd0;
//dat_o <= 32'd0;
ack_o <= 1'b0;
s_dat_o <= 32'd0;
dat_o <= 32'd0;
ack_o <= 1'b0;
end
else
begin
// s_dat_o <= s1_dat_o;
// dat_o[15:0] <= s_dat_o[15:0];
ack_o <= cyc_i & stb_i & ~ack_o;
s_dat_o <= s1_dat_o;
dat_o[15:0] <= s_dat_o[15:0];
ack_o <= stb_i & ~ack_o;
end
endmodule // s6_icap_wb

47
fpga/control_lib/settings_fifo_ctrl.v
View File

@@ -22,7 +22,8 @@ module settings_fifo_ctrl
parameter XPORT_HDR = 1, //extra transport hdr line
parameter PROT_DEST = 0, //protocol framer destination
parameter PROT_HDR = 1, //needs a protocol header?
parameter ACK_SID = 0 //stream ID for packet ACK
parameter ACK_SID = 0, //stream ID for packet ACK
parameter DEPTH = 6 //size of fifo in addr bit width
)
(
//clock and synchronous reset for all interfaces
@@ -75,16 +76,17 @@ module settings_fifo_ctrl
wire [63:0] in_command_ticks, out_command_ticks;
wire [31:0] in_command_hdr, out_command_hdr;
wire [31:0] in_command_data, out_command_data;
wire in_command_has_time, out_command_has_time;
wire command_fifo_full, command_fifo_empty;
wire command_fifo_read, command_fifo_write;
wire [15:0] command_fifo_occupied;
shortfifo #(.WIDTH(129)) command_fifo (
longfifo #(.WIDTH(128), .SIZE(DEPTH)) command_fifo (
.clk(clock), .rst(reset), .clear(clear),
.datain({in_command_ticks, in_command_hdr, in_command_data, in_command_has_time}),
.dataout({out_command_ticks, out_command_hdr, out_command_data, out_command_has_time}),
.datain({in_command_ticks, in_command_hdr, in_command_data}),
.dataout({out_command_ticks, out_command_hdr, out_command_data}),
.write(command_fifo_write), .full(command_fifo_full), //input interface
.empty(command_fifo_empty), .read(command_fifo_read) //output interface
.empty(command_fifo_empty), .read(command_fifo_read), //output interface
.occupied(command_fifo_occupied)
);
//------------------------------------------------------------------
@@ -95,13 +97,15 @@ module settings_fifo_ctrl
wire [31:0] in_result_data, out_result_data;
wire result_fifo_full, result_fifo_empty;
wire result_fifo_read, result_fifo_write;
wire [15:0] result_fifo_occupied;
shortfifo #(.WIDTH(64)) result_fifo (
longfifo #(.WIDTH(64), .SIZE(DEPTH)) result_fifo (
.clk(clock), .rst(reset), .clear(clear),
.datain({in_result_hdr, in_result_data}),
.dataout({out_result_hdr, out_result_data}),
.write(result_fifo_write), .full(result_fifo_full), //input interface
.empty(result_fifo_empty), .read(result_fifo_read) //output interface
.empty(result_fifo_empty), .read(result_fifo_read), //output interface
.occupied(result_fifo_occupied)
);
//------------------------------------------------------------------
@@ -139,7 +143,6 @@ module settings_fifo_ctrl
assign in_command_ticks = in_ticks_reg;
assign in_command_data = in_data_reg;
assign in_command_hdr = in_hdr_reg;
assign in_command_has_time = has_tsf_reg;
always @(posedge clock) begin
if (reset) begin
@@ -244,18 +247,24 @@ module settings_fifo_ctrl
always @(posedge clock)
vita_time_reg <= vita_time;
wire late;
wire late, now;
`ifndef FIFO_CTRL_NO_TIME
time_compare time_compare(
.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late));
.time_now(vita_time_reg), .trigger_time(command_ticks_reg), .late(late), .now(now));
`else
assign late = 1;
assign now = 1;
`endif
//these config flags are available only in the LOAD_CMD state (where we wait)
wire time_wait = out_command_hdr[9];
wire skip_late = out_command_hdr[10]; //TODO (implement)
reg cmd_was_late;
//action occurs in the event state and when there is fifo space (should always be true)
//the third condition is that all peripherals in the perfs signal are ready/active high
//the fourth condition is that is an event time has been set, action is delayed until that time
wire time_ready = (out_command_has_time)? late : 1;
wire time_ready = (time_wait)? (late || now) : 1;
wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_ready && time_ready;
assign command_fifo_read = action;
@@ -275,6 +284,7 @@ module settings_fifo_ctrl
command_ticks_reg <= out_command_ticks;
command_hdr_reg <= out_command_hdr;
command_data_reg <= out_command_data;
cmd_was_late <= late; //TODO do something with
end
EVENT_CMD: begin // poking and peeking happens here!
@@ -332,11 +342,14 @@ module settings_fifo_ctrl
localparam WRITE_VRT_SID = 2;
localparam WRITE_RB_HDR = 3;
localparam WRITE_RB_DATA = 4;
localparam WRITE_RB_DATA2 = 5;
localparam WRITE_RB_DATA3 = 6;
//the state for the start of packet condition
localparam WRITE_PKT_HDR = (PROT_HDR)? WRITE_PROT_HDR : WRITE_VRT_HDR;
reg [2:0] out_state;
reg [31:0] last_result_hdr;
assign out_valid = ~result_fifo_empty;
assign result_fifo_read = out_data[33] && writing;
@@ -344,9 +357,11 @@ module settings_fifo_ctrl
always @(posedge clock) begin
if (reset) begin
out_state <= WRITE_PKT_HDR;
last_result_hdr <= 32'b0;
end
else if (writing && out_data[33]) begin
out_state <= WRITE_PKT_HDR;
last_result_hdr <= out_result_hdr;
end
else if (writing) begin
out_state <= out_state + 1;
@@ -357,7 +372,7 @@ module settings_fifo_ctrl
//-- assign to output fifo interface
//------------------------------------------------------------------
wire [31:0] prot_hdr;
assign prot_hdr[15:0] = 16; //bytes in proceeding vita packet
assign prot_hdr[15:0] = 24; //bytes in proceeding vita packet
assign prot_hdr[16] = 1; //yes frame
assign prot_hdr[18:17] = PROT_DEST;
assign prot_hdr[31:19] = 0; //nothing
@@ -370,12 +385,14 @@ module settings_fifo_ctrl
WRITE_VRT_SID: out_data_int <= ACK_SID;
WRITE_RB_HDR: out_data_int <= out_result_hdr;
WRITE_RB_DATA: out_data_int <= out_result_data;
WRITE_RB_DATA2: out_data_int <= last_result_hdr;
WRITE_RB_DATA3: out_data_int <= {result_fifo_occupied, command_fifo_occupied};
default: out_data_int <= 0;
endcase //state
end
assign out_data[35:34] = 2'b0;
assign out_data[33] = (out_state == WRITE_RB_DATA);
assign out_data[33] = (out_state == WRITE_RB_DATA3);
assign out_data[32] = (out_state == WRITE_PKT_HDR);
assign out_data[31:0] = out_data_int;
@@ -389,7 +406,7 @@ module settings_fifo_ctrl
command_fifo_empty, command_fifo_full, //2
command_fifo_read, command_fifo_write, //2
addr, //8
strobe_reg, strobe, poke, out_command_has_time //4
strobe_reg, strobe, poke, time_wait //4
};
endmodule //settings_fifo_ctrl

10
fpga/coregen/pll_rx.v
View File

@@ -58,7 +58,6 @@
// CLK_OUT1 125.000 0.000 50.0 200.000 50.000
// CLK_OUT2 125.000 180.000 50.0 300.000 50.000
// CLK_OUT3 125.000 0.000 50.0 200.000 50.000
// CLK_OUT4 62.500 0.000 50.0 200.000 50.000
//
//----------------------------------------------------------------------------
// Input Clock Input Freq (MHz) Input Jitter (UI)
@@ -74,8 +73,7 @@ module pll_rx
// Clock out ports
output clk_rx,
output clk_rx_180,
output clk_to_mac,
output clk_rx_div2
output clk_to_mac
);
// Input buffering
@@ -97,7 +95,6 @@ module pll_rx
wire clkfb;
wire clk0;
wire clk180;
wire clkdv;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
@@ -123,7 +120,7 @@ module pll_rx
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.CLKDV (clkdv),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
@@ -154,9 +151,6 @@ module pll_rx
(.O (clk_to_mac),
.I (clk0));
BUFG clkout4_buf
(.O (clk_rx_div2),
.I (clkdv));
endmodule

27
fpga/coregen/pll_rx.xco
View File

@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Aug 2 17:45:53 2017
# Xilinx Core Generator version 13.1
# Date: Sat Jan 07 20:42:05 2012
#
##############################################################
#
@@ -12,16 +12,12 @@
#
##############################################################
#
# Generated from component: xilinx.com:ip:Clocking_Wizard:3.6
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET designentry = Advanced
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Other
@@ -31,12 +27,12 @@ SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Clocking_Wizard xilinx.com:ip:Clocking_Wizard:3.6
SELECT Clocking_Wizard family Xilinx,_Inc. 3.1
# END Select
# BEGIN Parameters
CSET calc_done=DONE
@@ -83,9 +79,9 @@ CSET clkout3_requested_phase=0.000
CSET clkout3_used=true
CSET clkout4_drives=BUFG
CSET clkout4_requested_duty_cycle=50.000
CSET clkout4_requested_out_freq=62.500
CSET clkout4_requested_out_freq=100.000
CSET clkout4_requested_phase=0.000
CSET clkout4_used=true
CSET clkout4_used=false
CSET clkout5_drives=BUFG
CSET clkout5_requested_duty_cycle=50.000
CSET clkout5_requested_out_freq=100.000
@@ -118,7 +114,6 @@ CSET dcm_clkfx_multiply=4
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
CSET dcm_clkgen_clk_out4_port=CLKDV
CSET dcm_clkgen_clkfx_divide=1
CSET dcm_clkgen_clkfx_md_max=0.000
CSET dcm_clkgen_clkfx_multiply=4
@@ -170,7 +165,7 @@ CSET mmcm_clkout3_duty_cycle=0.500
CSET mmcm_clkout3_phase=0.000
CSET mmcm_clkout3_use_fine_ps=false
CSET mmcm_clkout4_cascade=false
CSET mmcm_clkout4_divide=2
CSET mmcm_clkout4_divide=1
CSET mmcm_clkout4_duty_cycle=0.500
CSET mmcm_clkout4_phase=0.000
CSET mmcm_clkout4_use_fine_ps=false
@@ -212,7 +207,7 @@ CSET pll_clkout2_phase=0.000
CSET pll_clkout3_divide=1
CSET pll_clkout3_duty_cycle=0.500
CSET pll_clkout3_phase=0.000
CSET pll_clkout4_divide=2
CSET pll_clkout4_divide=1
CSET pll_clkout4_duty_cycle=0.500
CSET pll_clkout4_phase=0.000
CSET pll_clkout5_divide=1
@@ -258,4 +253,4 @@ CSET use_spread_spectrum=false
CSET use_status=false
# END Parameters
GENERATE
# CRC: 42b0e01c
# CRC: 681ed89a

3
fpga/top/UmTRX/Makefile.UmTRXv2
View File

@@ -97,8 +97,7 @@ MAP_PROPERTIES = \
"Map Effort Level" High \
"Extra Effort" Normal \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE \
"Starting Placer Cost Table (1-100)" 24
"Register Duplication" TRUE
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High \

121
fpga/top/UmTRX/Makefile.UmTRXv2_nosram
View File

@@ -1,121 +0,0 @@
#
# Copyright 2012 Fairwaves
#
##################################################
# Project Setup
##################################################
TOP_MODULE = u2plus_umtrx_v2
BUILD_DIR = $(abspath build$(ISE)_UmTRXv2_nosram)
##################################################
# Include other makefiles
##################################################
include ../Makefile.common
include ../../fifo/Makefile.srcs
include ../../control_lib/Makefile.srcs
include ../../sdr_lib/Makefile.srcs
include ../../serdes/Makefile.srcs
include ../../simple_gemac/Makefile.srcs
include ../../timing/Makefile.srcs
include ../../opencores/Makefile.srcs
include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extramfifo/Makefile.srcs
include ../../gpsdo/Makefile.srcs
##################################################
# Project Properties
##################################################
export PROJECT_PROPERTIES := \
family "Spartan6" \
device xc6slx75 \
package fgg484 \
speed -2 \
top_level_module_type "HDL" \
synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISE Simulator (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
"Display Incremental Messages" FALSE
##################################################
# Sources
##################################################
TOP_SRCS = \
capture_ddrlvds.v \
umtrx_core.v \
umtrx_tx_chain.v \
umtrx_rx_chain.v \
umtrx_router.v \
umtrx_packet_dispatcher.v \
coregen/chipscope_icon.v \
coregen/chipscope_icon.xco \
coregen/chipscope_ila.v \
coregen/chipscope_ila.xco \
coregen/fifo_short_2clk.v \
coregen/fifo_short_2clk.xco \
coregen/fifo_4k_2clk.v \
coregen/fifo_4k_2clk.xco \
coregen/fifo_axi_36.v \
coregen/fifo_axi_36.xco \
u2plus_umtrx_v2.v \
u2plus_umtrx_v2.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
$(GPSDO_SRCS)
##################################################
# Process Properties
##################################################
SYNTHESIZE_PROPERTIES = \
"Number of Clock Buffers" 8 \
"Pack I/O Registers into IOBs" Yes \
"Optimization Effort" High \
"Optimize Instantiated Primitives" TRUE \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
"Verilog Macros" "LVDS=1 | NO_SERDES=1 | UMTRX=1 | LMS602D_FRONTEND=1 | SPARTAN6=1 | LMS_DSP=1 | NUMDDC=2 | NUMDUC=2 | NO_EXT_FIFO=1 | INTERNAL_FIFOS=1"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Global Optimization" Speed\
"Optimization Strategy (Cover Mode)" Speed \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Perform Timing-Driven Packing and Placement" TRUE \
"Map Effort Level" High \
"Extra Effort" Normal \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High \
"Place & Route Extra Effort (Highest PAR level only)" NORMAL
STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
"Report Type" "Error Report"
GEN_PROG_FILE_PROPERTIES = \
"Configuration Rate" 6 \
"Create Binary Configuration File" TRUE \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" TRUE \
"Enable Outputs (Output Events)" 6
SIM_MODEL_PROPERTIES = ""

840
fpga/top/UmTRX/bootloader_umtrx.rmi
View File

@@ -1,5 +1,5 @@
defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_e2b30400_3a0b0b80_80f0a80c_82700b0b_0b0b0b0b;
defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80e2ff2d_88080b0b_80088408;
defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_dfcb0400_3a0b0b80_80eeb40c_82700b0b_0b0b0b0b;
defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80e0952d_88080b0b_80088408;
defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608;
defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608;
defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105;
@@ -18,438 +18,438 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_
defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981;
defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206;
defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608;
defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_94738306_0b0b80f0_71fc0608;
defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_d42d5050_0b0b80d9_88087575_80088408;
defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_862d5050_0b0b80db_88087575_80088408;
defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_a0738306_0b0b80ee_71fc0608;
defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ec2d5050_0b0b80d6_88087575_80088408;
defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_9e2d5050_0b0b80d8_88087575_80088408;
defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081;
defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081;
defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504;
defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80f0a40c_810b0b0b;
defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80eeb00c_810b0b0b;
defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552;
defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572;
defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff;
defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_dafc3f04_82813f80;
defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d8923f04_82813f80;
defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010;
defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04;
defparam bootram.RAM0.INIT_23=256'h800b80f1_840c82a0_0b0b80f1_8380800b_822ebd38_80f0a808_802ea438_80f0a408;
defparam bootram.RAM0.INIT_24=256'h0b80f188_80808280_f1840cf8_0b0b0b80_808080a4_8c0c04f8_800b80f1_880c8290;
defparam bootram.RAM0.INIT_25=256'h940b80f1_80c0a880_80f1840c_8c0b0b0b_80c0a880_f18c0c04_84800b80_0cf88080;
defparam bootram.RAM0.INIT_26=256'h70085252_80f0b008_5170a738_80f19033_04ff3d0d_80f18c0c_80e3b00b_880c0b0b;
defparam bootram.RAM0.INIT_27=256'h9034833d_810b80f1_5270ee38_08700852_2d80f0b0_f0b00c70_38841280_70802e94;
defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80f18008_3d0d0b0b_0d040480;
defparam bootram.RAM0.INIT_29=256'h0b81e088_80ce3881_0d685a79_0404ee3d_3f823d0d_0b0bf5d4_f180510b_040b0b80;
defparam bootram.RAM0.INIT_23=256'h800b80ef_900c82a0_0b0b80ef_8380800b_822ebd38_80eeb408_802ea438_80eeb008;
defparam bootram.RAM0.INIT_24=256'h0b80ef94_80808280_ef900cf8_0b0b0b80_808080a4_980c04f8_800b80ef_940c8290;
defparam bootram.RAM0.INIT_25=256'h940b80ef_80c0a880_80ef900c_8c0b0b0b_80c0a880_ef980c04_84800b80_0cf88080;
defparam bootram.RAM0.INIT_26=256'h70085252_80eebc08_5170a738_80ef9c33_04ff3d0d_80ef980c_80e0c40b_940c0b0b;
defparam bootram.RAM0.INIT_27=256'h9c34833d_810b80ef_5270ee38_08700852_2d80eebc_eebc0c70_38841280_70802e94;
defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80ef8c08_3d0d0b0b_0d040480;
defparam bootram.RAM0.INIT_29=256'h0b81e088_80ce3881_0d685a79_0404ee3d_3f823d0d_0b0bf5d4_ef8c510b_040b0b80;
defparam bootram.RAM0.INIT_2A=256'h7981e180_81e0f80c_0c890a0b_7981e598_81e5940c_e48c0c79_880c7981_0c7981e4;
defparam bootram.RAM0.INIT_2B=256'h81e2e80c_0c890a0b_7981e2a0_81e2980c_0c890a0b_7981e1d0_81e1c80c_0c890a0b;
defparam bootram.RAM0.INIT_2C=256'hae823f8c_0553425a_54973d84_08933d70_8238881a_8b6a2781_0c818839_7981e2f0;
defparam bootram.RAM0.INIT_2D=256'h7b34811c_5b5b7933_7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_af3f8008;
defparam bootram.RAM0.INIT_2C=256'ha9b43f89_0553425a_54973d84_08933d70_8238881a_8b6a2781_0c818839_7981e2f0;
defparam bootram.RAM0.INIT_2D=256'h7b34811c_5b5b7933_7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_a83f8008;
defparam bootram.RAM0.INIT_2E=256'h7c26ed38_811c5c88_79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26;
defparam bootram.RAM0.INIT_2F=256'h611d5b5b_805c7b1e_7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f;
defparam bootram.RAM0.INIT_30=256'h5a588379_84120859_3d0d686a_3d0d04ee_9ef83f94_7c26ef38_811c5c86_79337b34;
defparam bootram.RAM0.INIT_31=256'hf55778a3_99e63f80_80e3b451_8c537552_802e8c38_2e943875_0856758c_279c3877;
defparam bootram.RAM0.INIT_32=256'h75922682_ff981756_8818085d_8c5ba05c_d33fa057_e4985199_53a45280_268e3878;
defparam bootram.RAM0.INIT_33=256'h5c8c1808_cc3980da_08085e82_8bbe3f80_0480d55c_05567508_2980e698_e2387584;
defparam bootram.RAM0.INIT_34=256'hff065f82_800883ff_04b48b3f_05567508_2980e6e4_bc387584_75862682_5eff1e56;
defparam bootram.RAM0.INIT_35=256'h56b3c13f_2a545151_7107709f_30901a08_90180870_3f829a39_2251b3de_a4399218;
defparam bootram.RAM0.INIT_36=256'h18335682_81eb3995_3f80085f_8439b3ea_39b3e83f_b3e63f89_e43f8e39_828339b3;
defparam bootram.RAM0.INIT_37=256'h57577577_0b971933_18085280_1808538c_18335490_57765596_2e833884_577580f2;
defparam bootram.RAM0.INIT_38=256'h538c1933_953dea05_18337054_81b3398d_5f80d35c_ad3f8008_5776519a_2e833881;
defparam bootram.RAM0.INIT_39=256'h5c750284_d93f80c8_33525690_19538c19_3370548e_94398d18_3f80c95c_52568fa2;
defparam bootram.RAM0.INIT_3A=256'h08585675_80058c19_842980e7_80c23875_56758526_1833ff05_80ff3994_05b50534;
defparam bootram.RAM0.INIT_3B=256'h2980f194_9b397684_18227723_0ca23992_90180877_225fa939_5fae3976_08047608;
defparam bootram.RAM0.INIT_3C=256'hcc5c8c18_39785e80_80d25cad_08710c56_94059019_842980f1_568e3976_05700840;
defparam bootram.RAM0.INIT_3D=256'h887826ed_34811858_57753377_3d790557_58771996_0b833d5a_dc055480_0855943d;
defparam bootram.RAM0.INIT_3E=256'h77348118_57577533_963d7905_5a587719_800b833d_3ddc0554_5ca45594_38a439a0;
defparam bootram.RAM0.INIT_3F=256'h96a23f73_e4fc5254_75705380_04fd3d0d_3f943d0d_80519fb3_ed388380_58887826;
defparam bootram.RAM1.INIT_00=256'h5273518a_3f9039a0_9c3f9fc0_5272518a_80c05372_e82e8438_a0537387_802e9838;
defparam bootram.RAM1.INIT_01=256'h5280e5b0_8b813f89_80e59c51_0d829f3f_0d04f93d_883f853d_5273518a_903f80c0;
defparam bootram.RAM1.INIT_02=256'hb3e2939b_f1b00cf8_3f830b80_d05195cc_8c5280e5_9b548353_f8b3e293_5195dd3f;
defparam bootram.RAM1.INIT_03=256'h3f86d13f_9c0c82dd_800b81e0_81e09c0c_b43f810b_86cb3f87_0cbafe3f_0b80f1ac;
defparam bootram.RAM1.INIT_04=256'hb33f7452_80085586_3f87993f_883f89ee_80085194_3f87a53f_ee3f89fa_80085193;
defparam bootram.RAM1.INIT_05=256'h5198fa3f_52838080_be3f8c93_92813f98_52800851_3f838084_b43f8788_80085198;
defparam bootram.RAM1.INIT_06=256'h91ec3f8f_51a9a53f_3f838092_825198e5_85528380_f03f80d7_80845198_8ab25283;
defparam bootram.RAM1.INIT_07=256'h802e80c9_08578008_91f53f80_3dfc0551_89f53f89_80e5e451_3fbdee3f_f151bbc9;
defparam bootram.RAM1.INIT_08=256'h055180ce_52800890_5380e5f4_06ad3884_ee2e0981_567482fd_8e052256_38778008;
defparam bootram.RAM1.INIT_09=256'h3f883975_745186c1_3f88cb3f_525592e5_3f941770_fc5193f4_9a3880e5_cb3f8008;
defparam bootram.RAM1.INIT_0A=256'hbf3f8fac_95bc3f89_0d88943f_9e39fe3d_8ff43fff_3fa9a13f_983f9182_5276519e;
defparam bootram.RAM1.INIT_0B=256'h87b33f82_84528451_518dfd3f_c03f82ac_52805187_87e43f9f_9f528051_3f8abb3f;
defparam bootram.RAM1.INIT_0C=256'h8dd63f82_3f82ac51_90518799_e33f9052_82ac518d_5187a63f_3f885288_ac518df0;
defparam bootram.RAM1.INIT_0D=256'h13537280_8dba3fff_3f80e451_9c5186fd_c73f9f52_80e4518d_51878a3f_539f5280;
defparam bootram.RAM1.INIT_0E=256'h81e08056_04fb3d0d_0c843d0d_3f810b80_815186e1_853f9f52_529e5187_25df389f;
defparam bootram.RAM1.INIT_0F=256'h81528151_54888053_0c865590_833f8376_80e4518d_3f80760c_e4518d8c_83760c80;
defparam bootram.RAM1.INIT_10=256'h085280e7_949c3f80_82528151_54888053_3f865590_98519294_085280e7_94b43f80;
defparam bootram.RAM1.INIT_11=256'h85ea3ff8_823fff51_e7d05187_803d0d80_873d0d04_810b800c_3fac833f_b45191fc;
defparam bootram.RAM1.INIT_12=256'h34767081_54738a3d_75811757_7425b738_16565480_575874ff_7f7f5a57_3d0d7a7c;
defparam bootram.RAM1.INIT_13=256'h06548a51_800881ff_518a9b3f_7781ff06_3dfc0552_3482538a_8405a105_05583302;
defparam bootram.RAM1.INIT_14=256'hde567483_05335580_3d0d02a3_3d0d04fa_73800c8a_c1398154_802e8538_8bf23f73;
defparam bootram.RAM1.INIT_15=256'h3d0d7c57_3d0d04f9_ff893f88_5280d051_055381f7_54883dfc_883d3481_38dc5675;
defparam bootram.RAM1.INIT_16=256'h06705654_800881ff_5689bb3f_05337052_055202a7_53893dfc_893d3481_02ab0533;
defparam bootram.RAM1.INIT_17=256'h802e8338_70565473_0881ff06_87d43f80_7b527551_97387653_38807725_73802e9e;
defparam bootram.RAM1.INIT_18=256'h800881ff_51ffa03f_f75280d0_fc055381_8154883d_04fa3d0d_0c893d0d_81557480;
defparam bootram.RAM1.INIT_19=256'h83388156_2e098106_567480de_883d3356_9539800b_5185b83f_3880e7dc_0655748a;
defparam bootram.RAM1.INIT_1A=256'h883d2270_51fee03f_fc5280d0_fc055381_8254893d_04f93d0d_0c883d0d_75557480;
defparam bootram.RAM1.INIT_1B=256'h70565480_7a575781_fa3d0d78_893d0d04_800c5656_83ffff06_80290570_882a7182;
defparam bootram.RAM1.INIT_1C=256'h80558113_ff2e8338_33527181_38805471_70802e83_70335252_9e387217_53727627;
defparam bootram.RAM1.INIT_1D=256'hb8348653_810b80f1_04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974;
defparam bootram.RAM1.INIT_1E=256'h0b80f1b8_74bd3881_f1b83355_f93d0d80_843d0d04_80c6f93f_80f0b851_80e88052;
defparam bootram.RAM1.INIT_1F=256'h527551fe_2e9d3886_06557480_800881ff_51fdcc3f_825280d0_3d705456_34865487;
defparam bootram.RAM1.INIT_20=256'h0c893d0d_f0b80b80_c6ae3f80_f0b85180_53755280_748d3886_81ff0655_f33f8008;
defparam bootram.RAM1.INIT_21=256'h0b80f1b4_74b93881_f1b43355_fb3d0d80_f0b40c04_e7fc0880_f1b43480_04810b80;
defparam bootram.RAM1.INIT_22=256'h52873dfc_2e993884_06557480_800881ff_51fcec3f_8c5280d0_3dfc0553_34845487;
defparam bootram.RAM1.INIT_23=256'h04fb3d0d_0c873d0d_f0b40b80_f0b40c80_86387580_ff065574_3f800881_0551fe90;
defparam bootram.RAM1.INIT_24=256'hf0b40c81_38750880_74802e8d_81ff0655_b23f8008_80d051fb_75538c52_77568454;
defparam bootram.RAM1.INIT_25=256'hc0ac0c89_0ca60b81_0b81c080_940c80eb_990b81c0_873d0d04_3474800c_0b80f1b4;
defparam bootram.RAM1.INIT_26=256'ha00c81c0_820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0;
defparam bootram.RAM1.INIT_27=256'h882bbe80_803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081;
defparam bootram.RAM1.INIT_28=256'h81065151_70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107;
defparam bootram.RAM1.INIT_29=256'hbc080607_067180f1_73097375_3f803d0d_0d7251f8_ff39803d_823d0d04_5170f138;
defparam bootram.RAM1.INIT_2A=256'h077080f1_f1c00806_75067180_0d730973_0d04803d_0c51823d_0c81e08c_7080f1bc;
defparam bootram.RAM1.INIT_2B=256'h800c843d_81c73f72_53538051_3d0d7470_af3f04fe_3d0d0481_980c5182_c00c81e0;
defparam bootram.RAM1.INIT_2C=256'h06545472_337081ff_79565674_fb3d0d77_833d0d04_5181b63f_0d8a5280_0d04ff3d;
defparam bootram.RAM1.INIT_2D=256'h3d0d7352_3d0d04ff_0b800c87_3fe53980_52558191_ff065376_81157481_802e9038;
defparam bootram.RAM1.INIT_2E=256'h0b800c84_80e73f80_8a527251_53ffbd3f_76537052_fe3d0d74_833d0d04_8051cd3f;
defparam bootram.RAM1.INIT_2F=256'h1234823d_3380f0c0_51028f05_803d0d72_833d0d04_8051dd3f_3d0d7352_3d0d04ff;
defparam bootram.RAM1.INIT_30=256'hfe3d0d80_833d0d04_720c5351_88057022_751080e8_82908005_0d73a029_0d04ff3d;
defparam bootram.RAM1.INIT_31=256'h38843d0d_827325e5_3f811353_527251ce_f0c41333_51c63f80_13335272_5380f0c0;
defparam bootram.RAM1.INIT_32=256'h87388d52_2e098106_33537281_80f0c014_81069538_748a2e09_76785654_04fc3d0d;
defparam bootram.RAM1.INIT_33=256'h04fe3d0d_0c863d0d_38748c15_72802ef8_84140853_90800554_73a02982_7351de3f;
defparam bootram.RAM1.INIT_34=256'h0d04ff3d_800c843d_12085372_2e853890_ff537080_11085252_90800588_74a02982;
defparam bootram.RAM1.INIT_35=256'h800b81a8_840c5181_882a81a8_a8800c70_81ff0681_f0cc2270_a8880c80_0d800b81;
defparam bootram.RAM1.INIT_36=256'h8386d052_2e81b038_81517280_33565455_88059b05_0d777902_0d04fc3d_880c833d;
defparam bootram.RAM1.INIT_37=256'h39731081_7151818f_5271e938_8c38ff12_5170802e_81065151_70862a70_81a89008;
defparam bootram.RAM1.INIT_38=256'h5170802e_81065151_70812a70_81a89008_8386d052_81a8900c_0c81900b_0781a88c;
defparam bootram.RAM1.INIT_39=256'h80c63872_5170802e_32515151_81067081_70872a70_81a89008_5271e938_8738ff12;
defparam bootram.RAM1.INIT_3A=256'h812a7081_a8900870_86d05281_a8900c83_a0517081_812e8338_80e85172_802ebd38;
defparam bootram.RAM1.INIT_3B=256'h1353c039_055734ff_70757081_a88c0851_71e93881_38ff1252_70802e87_06515151;
defparam bootram.RAM1.INIT_3C=256'h33565455_88059b05_0d777902_0d04fc3d_800c863d_a8900c70_80c00b81_81518839;
defparam bootram.RAM1.INIT_3D=256'h715181ad_5271e938_8c38ff12_5170802e_81065151_70862a70_81a89008_8386d052;
defparam bootram.RAM1.INIT_3E=256'ha8900870_86d05281_a8900c83_90517081_2e843881_d0517280_a88c0c81_39731081;
defparam bootram.RAM1.INIT_3F=256'h06708132_872a7081_a8900870_71e93881_38ff1252_70802e87_06515151_812a7081;
defparam bootram.RAM2.INIT_00=256'h83389051_5172812e_8c0c80d0_743381a8_2e80d138_db387280_70802e80_51515151;
defparam bootram.RAM2.INIT_01=256'h125271e9_2e8738ff_51517080_70810651_0870812a_5281a890_0c8386d0_7081a890;
defparam bootram.RAM2.INIT_02=256'h55ffab39_15ff1454_2e8e3881_51517080_81325151_70810670_0870872a_3881a890;
defparam bootram.RAM2.INIT_03=256'h74259b38_54805372_fd3d0d75_863d0d04_5170800c_a8900c80_80c00b81_81518a39;
defparam bootram.RAM2.INIT_04=256'h0d04fa3d_e239853d_38811353_8f7127f1_515181cb_08707331_5281b8ac_81b8ac08;
defparam bootram.RAM2.INIT_05=256'h86388151_5271802e_38728306_0652718a_91387583_55575771_72830655_0d787a7c;
defparam bootram.RAM2.INIT_06=256'h811454e9_0c525452_12700872_2b771177_94387382_55737527_822a7255_f8e83f72;
defparam bootram.RAM2.INIT_07=256'h8f0680e8_f8f53f72_54515353_e8941133_708f0680_7470842a_04fe3d0d_39883d0d;
defparam bootram.RAM2.INIT_08=256'hef0b8280_8280800c_0c81e00b_0b828088_ff3d0dff_843d0d04_53f8e83f_94113352;
defparam bootram.RAM2.INIT_09=256'hf138833d_51708025_540cff11_72708405_8751a3b2_80f3f452_82808c0c_840cff0b;
defparam bootram.RAM2.INIT_0A=256'h55747606_80f3f455_8053810b_06585152_808c0871_08700982_0d828088_0d04fb3d;
defparam bootram.RAM2.INIT_0B=256'h53877325_76105755_81138415_8c0c8f39_2d748280_73085271_8f387251_5271802e;
defparam bootram.RAM2.INIT_0C=256'h722b7009_710c5181_f3f40575_71842980_87269f38_0d735271_0d04ff3d_dc38873d;
defparam bootram.RAM2.INIT_0D=256'h0881e0c4_05227470_3d0d0292_0d0404ff_5152833d_80880c53_70720682_82808808;
defparam bootram.RAM2.INIT_0E=256'h70802ef3_84065151_b8a00870_e0c00c81_0d810b81_0d04803d_c80c833d_0c5281e0;
defparam bootram.RAM2.INIT_0F=256'h81b8a008_802e9338_06545272_a0087081_3d0d81b8_3d0d04fe_e0c00c82_38820b81;
defparam bootram.RAM2.INIT_10=256'he8a451f7_2e8b3880_51527180_2a708106_9a397181_81808052_710c5353_7571902a;
defparam bootram.RAM2.INIT_11=256'h802ef238_06515170_087080c0_0d81b8a0_0d04803d_800c843d_3f725271_9a3fffa6;
defparam bootram.RAM2.INIT_12=256'hb8a00870_c00c5281_880781e0_2270902b_0d028e05_0d04ff3d_800c823d_8180800b;
defparam bootram.RAM2.INIT_13=256'h2e8638ba_80537280_3d0d7554_3d0d04fd_e0c00c83_38840b81_70802ef3_90065151;
defparam bootram.RAM2.INIT_14=256'h77831133_04fb3d0d_38853d0d_857327e6_3f811353_5252fcd9_72147033_51f5ec3f;
defparam bootram.RAM2.INIT_15=256'h7e616302_f63d0d7c_873d0d04_5180ed3f_5680e8a8_54703353_55811133_56821133;
defparam bootram.RAM2.INIT_16=256'h52ad5178_2e8a3879_8f387580_57768025_5f5d5b59_9f2a515b_33703070_9005bb05;
defparam bootram.RAM2.INIT_17=256'h77527651_51ffbd3f_953f8008_527651b3_54805377_38795578_77772694_2d763057;
defparam bootram.RAM2.INIT_18=256'h823d0d04_51f4d43f_028b0533_04803d0d_2d8c3d0d_05335178_0880e8b4_b3ad3f80;
defparam bootram.RAM2.INIT_19=256'hd1387681_75802e81_ff065757_78337081_915c5a58_055208a6_3d707084_f73d0d8c;
defparam bootram.RAM2.INIT_1A=256'h24a03875_387580f0_f02e80fb_57597580_81197033_0680db38_a52e0981_ff065675;
defparam bootram.RAM2.INIT_1B=256'h8b397580_80c63881_7580e42e_38819539_802e819e_248a3875_387580e3_80e32eb9;
defparam bootram.RAM2.INIT_1C=256'h39778419_ba3880ec_7580f82e_3880f539_f32e80db_8b387580_7580f524_f52eac38;
defparam bootram.RAM2.INIT_1D=256'h80539039_55a69154_52595680_84197108_80da3977_7551792d_59568052_83123352;
defparam bootram.RAM2.INIT_1E=256'h55a69154_52595680_84197108_52923977_5481538a_8055a691_08525956_77841971;
defparam bootram.RAM2.INIT_1F=256'h52767081_2e8e3880_33567580_59595676_84197108_3f9e3977_7551fdd0_80539052;
defparam bootram.RAM2.INIT_20=256'h04803d0d_81e5e40c_0d048a0b_800c8b3d_a339800b_811959fe_792dec39_05583351;
defparam bootram.RAM2.INIT_21=256'h88059b05_0d797b02_0d04fc3d_ef38823d_51515170_32708106_708c2a81_81b8b408;
defparam bootram.RAM2.INIT_22=256'h81065151_72822a70_810a0752_2e863871_54547080_06555557_7b077281_3372982b;
defparam bootram.RAM2.INIT_23=256'he5ec0c74_e80c7081_3f7181e5_5151ffa9_3179712b_0752a074_3871820a_70802e86;
defparam bootram.RAM2.INIT_24=256'h3d0d04fc_70800c86_06515252_80087072_ff0581b8_3f81742b_9338ff95_5174802e;
defparam bootram.RAM2.INIT_25=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678;
defparam bootram.RAM2.INIT_26=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e;
defparam bootram.RAM2.INIT_27=256'h80720c88_d8528951_3d0d80f1_3d0d04ff_d00c5485_700880f1_b4de3f76_80f1c851;
defparam bootram.RAM2.INIT_28=256'h52702254_80f1d452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252;
defparam bootram.RAM2.INIT_29=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525289_38811288_72742e8e;
defparam bootram.RAM2.INIT_2A=256'h80f1d455_80f1d80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653;
defparam bootram.RAM2.INIT_2B=256'h73237684_e9b63f75_7525eb38_14545589_38811588_71802e8f_88155552_55557308;
defparam bootram.RAM2.INIT_2C=256'h88055291_7353923d_54b3ad3f_3dd60552_933d5392_0d867054_0d04f13d_140c883d;
defparam bootram.RAM2.INIT_2D=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_b39e3f90_3ddc0551;
defparam bootram.RAM2.INIT_2E=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180;
defparam bootram.RAM2.INIT_2F=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4;
defparam bootram.RAM2.INIT_30=256'hf5803f91_98840551_80c02982_d4055269_ac53913d_05be0523_23800284_800b913d;
defparam bootram.RAM2.INIT_31=256'h80f1c852_8b3f8653_f20551b2_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8;
defparam bootram.RAM2.INIT_32=256'h5a800b9b_08800858_f7d83f80_80e20523_22028405_0280f205_51b1fd3f_9a3df805;
defparam bootram.RAM2.INIT_33=256'ha33d0883_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143;
defparam bootram.RAM2.INIT_34=256'h3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684_05fc0640;
defparam bootram.RAM2.INIT_35=256'hd051eea3_883880e8_5473802e_16088306_738c3894_73830654_802e9a38_75085473;
defparam bootram.RAM2.INIT_36=256'hac3878bf_778025ff_ff195957_05570817_3f757084_7651f3d2_94160852_3f750853;
defparam bootram.RAM2.INIT_37=256'h943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f6de_c0597882_26843880;
defparam bootram.RAM2.INIT_38=256'h80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405_1f94055a;
defparam bootram.RAM2.INIT_39=256'h5cfae03f_933d7052_80538a52_08466847_2380f1d0_0580d205_23800284_5a79963d;
defparam bootram.RAM2.INIT_3A=256'hff065a79_3f800881_5c5e8ac8_983d7053_913d7053_80d20523_79028405_8008095a;
defparam bootram.RAM2.INIT_3B=256'h5d94557b_60586b57_7f5a6d59_3fa93902_ac3fec92_3f7a51f6_fc51f7b8_923880e8;
defparam bootram.RAM2.INIT_3C=256'h3d0d04f7_fd893f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d_54908053;
defparam bootram.RAM2.INIT_3D=256'h028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522_3d0d7f58;
defparam bootram.RAM2.INIT_3E=256'h0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854_05237756;
defparam bootram.RAM2.INIT_3F=256'hd33f8653_b60523e7_81028405_05b50534_34840284_860b8f3d_05b20523_90800284;
defparam bootram.RAM3.INIT_00=256'h53805294_aeaa3f86_3df20551_80085294_a33f8453_aeba3fe8_3dec0551_80085294;
defparam bootram.RAM3.INIT_01=256'he4055490_9c55943d_80578056_80598058_0843025c_873f8008_afb73fe8_3df60551;
defparam bootram.RAM3.INIT_02=256'h04d93d0d_3f943d0d_ef38fbcb_5b867b26_7a34811b_e8c81b33_7a1c5a80_8653805b;
defparam bootram.RAM3.INIT_03=256'h5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d_aa3d088e;
defparam bootram.RAM3.INIT_04=256'h225a7990_e238821b_09810686_5a79812e_ee397a22_f5963f86_80e9ac51_8d387952;
defparam bootram.RAM3.INIT_05=256'h2e098106_225a7981_c638861b_09810686_798c842e_841b225a_0686d438_802e0981;
defparam bootram.RAM3.INIT_06=256'ha93dffa8_80f1d052_08438453_87fd3f80_1d70525f_88853fa8_1d705240_86b9389e;
defparam bootram.RAM3.INIT_07=256'h22a13d23_acca3f7a_c8527951_865380f1_38a73d5a_8008868f_3f80085c_0551abec;
defparam bootram.RAM3.INIT_08=256'h84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe_821b2202;
defparam bootram.RAM3.INIT_09=256'h02818e05_5aac893f_3dea0552_547f53aa_973f8470_e40551ac_7952a93d_05238653;
defparam bootram.RAM3.INIT_0A=256'h7a527e51_3d5f8653_abee3f9e_3df40551_537f52a9_abfa3f79_1d527a51_5b865398;
defparam bootram.RAM3.INIT_0B=256'h79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59_abe23f02;
defparam bootram.RAM3.INIT_0C=256'h708c2a43_901d7022_0684e438_802e0981_ee397d90_f9993f84_7c26ef38_811c5c86;
defparam bootram.RAM3.INIT_0D=256'h861b2280_0684c038_852e0981_06515a79_882a708f_84d13879_2e098106_5b5b6084;
defparam bootram.RAM3.INIT_0E=256'h7e901c62_8338815e_fb3f8008_821d51a9_80e8c852_7e5e8653_7e84b438_ffff065f;
defparam bootram.RAM3.INIT_0F=256'h1d529c1d_84813888_387b802e_815c7d87_80088338_5ca9e53f_5470535b_5580f1d0;
defparam bootram.RAM3.INIT_10=256'hde388c1b_09810683_387f912e_812e81bb_405d407f_1c22ec11_891b3382_5184b83f;
defparam bootram.RAM3.INIT_11=256'h83bd39ac_51f1e53f_5280e9cc_3879537d_7d7a2e8f_5d5d4240_1f841122_087a08a4;
defparam bootram.RAM3.INIT_12=256'h499a3d99_993d237f_a6387a22_08802e83_80084280_5df5c33f_1d22535d_1de41d82;
defparam bootram.RAM3.INIT_13=256'h3d236047_821b2297_51a9cd3f_5379527f_9c3d4088_51a9d93f_537d5279_3d5f5a88;
defparam bootram.RAM3.INIT_14=256'h3d5e5c7b_7c557e84_af3f7b56_527d51a9_3f885379_7951a9b8_ffb40552_8853a93d;
defparam bootram.RAM3.INIT_15=256'h34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b_1d7c1f5b;
defparam bootram.RAM3.INIT_16=256'h8a387d88_427d832e_7033405b_1b08a41e_82ad398c_085a792d_38618405_887b26ef;
defparam bootram.RAM3.INIT_17=256'h5c5e5c79_1e891233_ac1d80c0_0681a238_832e0981_1a335a79_82953981_2e81bb38;
defparam bootram.RAM3.INIT_18=256'h7c229b3d_8c1c085a_2e80fe38_41800880_813f8008_7c2251f4_0681f438_912e0981;
defparam bootram.RAM3.INIT_19=256'h873f901c_527f51a8_4088537d_933f963d_527d51a8_5e88537a_3d9b3d5c_23794b98;
defparam bootram.RAM3.INIT_1A=256'ha7e63f7e_7a527d51_ef3f8853_527a51a7_a93dcc05_794d8853_229d3d23_085a821d;
defparam bootram.RAM3.INIT_1B=256'h7f1b5a79_ef38805b_5c887c26_7b34811c_5b5b7933_7b1d7c1f_843d5e5c_567e557e;
defparam bootram.RAM3.INIT_1C=256'hde39ac1d_e3d53f80_2d80e951_05085a79_ef386084_5b887b26_1c34811b_33028405;
defparam bootram.RAM3.INIT_1D=256'h3d23861a_841a2296_80ce0523_7e028405_80cd0534_7e028405_7e953d34_e41d5d5d;
defparam bootram.RAM3.INIT_1E=256'h51f1c03f_812a527c_8008537b_5bf1cc3f_943d7052_7e536052_80d20523_22028405;
defparam bootram.RAM3.INIT_1F=256'h3d0d04fc_f5f73fa9_7f526151_7d547a53_7b567c55_80ce0523_79028405_8008095a;
defparam bootram.RAM3.INIT_20=256'h53517075_71088c13_ac545651_700880f2_27a43876_55537274_80f2a408_3d0d800b;
defparam bootram.RAM3.INIT_21=256'h3d0d7779_3d0d04fb_70800c86_e738ff51_53737326_8b398113_85387251_2e098106;
defparam bootram.RAM3.INIT_22=256'h0c8e3980_1480f2a4_26893881_08547387_3880f2a4_088025ba_ffb93f80_71535755;
defparam bootram.RAM3.INIT_23=256'h53755280_0c515486_80f2ac12_822b7608_73101470_f2a80c54_11870680_f2a80881;
defparam bootram.RAM3.INIT_24=256'h873d0d04_51a5a93f_80f2b005_52738429_54865375_10800805_94398008_f2b01451;
defparam bootram.RAM3.INIT_25=256'h80f2b005_53738429_08055486_80081080_08249938_80547380_51fed83f_fd3d0d75;
defparam bootram.RAM3.INIT_26=256'h902b0782_71982b71_33811233_3d0d7570_3d0d04fd_73800c85_ff3f8154_527651a4;
defparam bootram.RAM3.INIT_27=256'h7f80f38c_f93d0d7d_853d0d04_54565452_800c5253_16337107_2b720783_14337088;
defparam bootram.RAM3.INIT_28=256'hf3901433_80e23880_54738326_72315256_8b3d2270_83ffff06_76af3873_22565957;
defparam bootram.RAM3.INIT_29=256'h22707231_ff068d3d_397383ff_942380c8_387680f3_547380d0_982c5151_70982b70;
defparam bootram.RAM3.INIT_2A=256'h3d5280f3_3888538a_555573a4_70982c51_3370982b_80f39016_8326b538_58565475;
defparam bootram.RAM3.INIT_2B=256'h893d0d04_1555ec39_e1cb3f81_53547551_74177033_78279138_3f735574_9451a3e0;
defparam bootram.RAM3.INIT_2C=256'h810680f3_2c813270_c0398275_59565680_7080f394_f38c2380_a6052280_f93d0d02;
defparam bootram.RAM3.INIT_2D=256'h729c180c_7298180c_34727723_a2397574_38ff7434_72802e86_5b565153_90178118;
defparam bootram.RAM3.INIT_2E=256'h70837827_77078025_55753070_18585677_3f8116a0_0551eeed_f38c2275_b9f85280;
defparam bootram.RAM3.INIT_2F=256'h51575775_2b70982c_1b337098_5b80f390_f53d0d80_893d0d04_72ffaf38_06515153;
defparam bootram.RAM3.INIT_30=256'h3f8008ff_7a51e0e1_f39c195a_80d83880_5c788f26_9805085a_80f3940b_81d63875;
defparam bootram.RAM3.INIT_31=256'h59515858_25075351_80257180_32703072_7030728d_06708a32_800881ff_2e80c738;
defparam bootram.RAM3.INIT_32=256'h940b9c05_800b80f3_80f3ac0c_ac088105_5c3480f3_7a708105_38815c77_76802e83;
defparam bootram.RAM3.INIT_33=256'h08811180_940b9c05_993880f3_80e6387b_ac08802e_af3880f3_8f7927ff_0c811959;
defparam bootram.RAM3.INIT_34=256'h98050855_80f3940b_802eaf38_94225675_cb3880f3_fa762780_050c5681_f3940b9c;
defparam bootram.RAM3.INIT_35=256'h80f38c22_7726ef38_81175788_17337634_5680f394_59577618_800b833d_80f39c54;
defparam bootram.RAM3.INIT_36=256'h7b27fe91_811b5b83_0b9c050c_0b80f394_98050c80_80f3940b_da3f800b_7b0551f1;
defparam bootram.RAM3.INIT_37=256'h528151ea_ff065384_9054759f_c4238555_567580f3_029e0522_04fb3d0d_388d3d0d;
defparam bootram.RAM3.INIT_38=256'h800b8813_0c73710c_70840553_e5ea8071_70525298_0d80f3d0_0d04ff3d_b53f873d;
defparam bootram.RAM3.INIT_39=256'hb084088a_81ec3881_5372802e_81065151_70812a70_81b08008_04f93d0d_0c833d0d;
defparam bootram.RAM3.INIT_3A=256'h81be3872_f2e17324_801453f9_0ce79a96_0b81b080_82fb3f81_f8055254_3dfc1154;
defparam bootram.RAM3.INIT_3B=256'h55807325_2b595154_982c7683_70982b70_80f0d833_80f3bc0c_81b63873_868d9f24;
defparam bootram.RAM3.INIT_3C=256'h2980f0d4_f0d40888_81863980_80f3d00c_f0d40c73_d8347580_537280f0_9638ff15;
defparam bootram.RAM3.INIT_3D=256'h90752587_515380ce_71315858_98e5ea80_0c70862a_2a80f0d4_84057083_08317611;
defparam bootram.RAM3.INIT_3E=256'h80f3d008_80f3d80c_d8081570_f05580f3_8538ffb1_ffb1f025_558c3974_3880ce90;
defparam bootram.RAM3.INIT_3F=256'h2586388f_538fff73_2c515255_05711187_29729029_0c7680c0_7780f3d0_7731882b;
defparam bootram.RAM4.INIT_00=256'h7680f3b8_53fdca3f_ffff0652_08137083_5380f3d4_8438f081_72f08125_ff538a39;
defparam bootram.RAM4.INIT_01=256'h53e5e13f_80e9f052_ff067053_800883ff_0dd69a3f_0d04fe3d_b40c893d_0c7780f3;
defparam bootram.RAM4.INIT_02=256'h883fbea5_0c7251fd_0b80f3bc_f0d83480_53820b80_84389080_2e098106_7283ffff;
defparam bootram.RAM4.INIT_03=256'h843d0d04_5180ca3f_5280f3b8_0c80f3b4_0b81b080_fd9c3f81_a13f7251_528151e2;
defparam bootram.RAM4.INIT_04=256'hc83f833d_347151fc_0b80f0d8_fcf43f82_22705252_0d028e05_0c04ff3d_7180f3c0;
defparam bootram.RAM4.INIT_05=256'h0c0480f3_f3b80880_800c0480_80f0d408_08800c04_0480f3bc_c422800c_0d0480f3;
defparam bootram.RAM4.INIT_06=256'h70722e93_54545454_81b8a808_ac08720c_a80881b8_757781b8_04fd3d0d_b408800c;
defparam bootram.RAM4.INIT_07=256'hd05382e0_3d0d8386_3d0d04fe_71740c85_740c8439_26863870_fffffffe_38720887;
defparam bootram.RAM4.INIT_08=256'h3f843d0d_8051d9c7_e93880ea_ff135372_802e8e38_51515271_2a708106_90087088;
defparam bootram.RAM4.INIT_09=256'he0900870_86d05382_07555583_0780c080_7c8c8006_7a80ff06_029b0533_04fc3d0d;
defparam bootram.RAM4.INIT_0A=256'he0800c73_8a3f7882_ea8051d9_72e93880_38ff1353_71802e8e_06515152_882a7081;
defparam bootram.RAM4.INIT_0B=256'h86d05382_2ea93883_74527480_82e0900c_73828007_82e0980c_7781ff06_82e0900c;
defparam bootram.RAM4.INIT_0C=256'hc63f82e0_ea8051d8_72e93880_38ff1353_71802e8e_06515152_882a7081_e0900870;
defparam bootram.RAM4.INIT_0D=256'h8051fee1_80538052_80558854_e0940c88_0d810b82_0d04fc3d_800c863d_80085271;
defparam bootram.RAM4.INIT_0E=256'h800c863d_0881ff06_fecb3f80_81528151_548a8053_88805590_04fc3d0d_3f863d0d;
defparam bootram.RAM4.INIT_0F=256'h80088132_3d0dca3f_3d0d0480_feaf3f86_81528051_88548653_0d888055_0d04fc3d;
defparam bootram.RAM4.INIT_10=256'hfb3d0d77_823d0d04_802ef438_ff065170_3f800881_803d0deb_823d0d04_8106800c;
defparam bootram.RAM4.INIT_11=256'h53815280_069b0a07_75fe9b0a_8055a054_ffb43f88_9b38dd3f_75800826_5685923f;
defparam bootram.RAM4.INIT_12=256'h81ff2681_57805573_ff115657_80cb3d08_80c93d08_ffba3d0d_873d0d04_51fdde3f;
defparam bootram.RAM4.INIT_13=256'h3f755380_52549ae1_52883d70_805381ff_81a73882_73800826_5484ce3f_b4387517;
defparam bootram.RAM4.INIT_14=256'h900c76fe_800b82e0_e0980c88_e63f7482_fed43ffc_3ffefd3f_735199bc_cb3d0852;
defparam bootram.RAM4.INIT_15=256'he0900cfc_8aa00b82_82e0900c_0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680;
defparam bootram.RAM4.INIT_16=256'hfe881570_e0880c54_15700882_0c54fe84_0882e08c_fe801570_3d558f56_b63f80c8;
defparam bootram.RAM4.INIT_17=256'h900cfbf7_800b82e0_e0900c8a_88800b82_e0800c54_15700882_0c54fe8c_0882e084;
defparam bootram.RAM4.INIT_18=256'h04f93d0d_80c83d0d_5574800c_e0980c81_38800b82_8025ffbc_16565675_3fff1690;
defparam bootram.RAM4.INIT_19=256'h387581ff_802e80c3_38815774_082680cb_80577380_56838a3f_12575a56_797b7d72;
defparam bootram.RAM4.INIT_1A=256'heb3f7316_527551fd_54775373_27833876_55577675_80743175_2ea23882_06547380;
defparam bootram.RAM4.INIT_1B=256'h3f815776_dc39fd8c_38828054_807527e1_38745482_74802e8e_31575956_74197676;
defparam bootram.RAM4.INIT_1C=256'h74279038_9c3f8008_73135482_802e8d38_56545573_0d76787a_0d04fc3d_800c893d;
defparam bootram.RAM4.INIT_1D=256'h5281ec3f_ff165651_30707406_fa3f8008_0ca63981_160c8075_0c800b84_800b8816;
defparam bootram.RAM4.INIT_1E=256'h54fc983f_fd3d0d75_863d0d04_51fcc93f_88160c71_84160c71_760c7406_80083072;
defparam bootram.RAM4.INIT_1F=256'h14088008_81b13f88_082e9438_14088415_38815388_71802e9f_06705452_800881ff;
defparam bootram.RAM4.INIT_20=256'h0a538152_a05481f9_0d888055_0d04fc3d_800c853d_3f805372_0c51fc94_05708816;
defparam bootram.RAM4.INIT_21=256'h38d43f80_557480c2_80f3dc08_04fb3d0d_0c863d0d_800a0680_3f8008fe_8151f9fd;
defparam bootram.RAM4.INIT_22=256'h2e833881_c73f73a0_585154dd_80ea9c54_70567155_0881ff06_81ff0680_08882a70;
defparam bootram.RAM4.INIT_23=256'hdc0c80f3_397580f3_d2c53f9c_80eab451_802e8a38_81065473_2e933874_557380c0;
defparam bootram.RAM4.INIT_24=256'h0d04ff91_800c873d_cb9a3f74_51dd8d3f_5280ead4_278d3874_55558274_dc08ea11;
defparam bootram.RAM4.INIT_25=256'h2b800c04_810b8008_04fefa3f_082b800c_3f810b80_800c04f2_eade0533_3f800880;
defparam bootram.RAM4.INIT_26=256'h882b82e0_e0840c7c_0c8b0b82_0b82e090_980c8880_800b82e0_56f8b03f_f63d0d7d;
defparam bootram.RAM4.INIT_27=256'h54737627_3f7e5580_900cf7ff_a80b82e0_e0900c8a_88a80b82_82e0980c_800c810b;
defparam bootram.RAM4.INIT_28=256'h085982e0_5882e088_82e08c08_0cf7e43f_0b82e090_900c8a80_800b82e0_80d33888;
defparam bootram.RAM4.INIT_29=256'h27913871_80527173_83387053_53707327_31525790_883d7675_e080085b_84085a82;
defparam bootram.RAM4.INIT_2A=256'h3d0d04ea_e0980c8c_39800b82_1454ffa9_52ec3972_57348112_75708105_17517033;
defparam bootram.RAM4.INIT_2B=256'h547381ff_17703351_05575574_0284059d_fed23f80_c0526851_70545780_3d0d883d;
defparam bootram.RAM4.INIT_2C=256'h548b3981_06853881_992e0981_51547381_74167033_81069438_81aa2e09_2e9d3873;
defparam bootram.RAM4.INIT_2D=256'hfe823f80_82527751_3d705454_fb3d0d86_983d0d04_5473800c_27d13880_1555be75;
defparam bootram.RAM4.INIT_2E=256'h0d04810b_800c873d_38815574_09810683_8008752e_5192853f_eaf85273_55825380;
defparam bootram.RAM4.INIT_2F=256'h80eb9c52_ff067053_3f800881_f23fca95_eafc51cf_f7c03f80_04fc3d0d_81e0940c;
defparam bootram.RAM4.INIT_30=256'h51818739_3880ebb4_51547388_70810651_08708d2a_3f81b8b4_8051c98b_55da9d3f;
defparam bootram.RAM4.INIT_31=256'ha63f8151_ec8051cf_2e9c3880_3f800880_0a51feaf_ba3f9880_ebd451cf_74b73880;
defparam bootram.RAM4.INIT_32=256'h51fed13f_398c800a_b05180ce_fa3f80ec_800a5183_3f745298_ac51d4ac_c8d13f82;
defparam bootram.RAM4.INIT_33=256'h80ed8451_51fcc53f_528c800a_5380ffff_3f838080_d851cef7_bd3880ec_8008802e;
defparam bootram.RAM4.INIT_34=256'h5183ac3f_3f805280_ac51d3dc_ced13f82_80ed9851_3ffed33f_ac51d3ec_cee13f82;
defparam bootram.RAM4.INIT_35=256'he82e8438_a0537387_3d0d7554_e00c04fd_047180f3_3f863d0d_b451cebb_883980ed;
defparam bootram.RAM4.INIT_36=256'h38735172_72802e85_f3e00853_ccdf3f80_72527251_51d8d53f_5280edd8_80c05373;
defparam bootram.RAM4.INIT_37=256'h72802e85_f3e00853_ccbb3f80_c0528051_ccc33f80_a0528051_04fe3d0d_2d853d0d;
defparam bootram.RAM4.INIT_38=256'h54815571_81065153_08862a70_3fff0b80_9a51cbb7_04fc3d0d_2d843d0d_38805172;
defparam bootram.RAM4.INIT_39=256'h388a5471_8280248a_2e9b3871_54718280_535580e4_08868006_38820b80_802e80ec;
defparam bootram.RAM4.INIT_3A=256'hea3f7188_528551ca_f23f8008_548451ca_2e8338ff_54718480_8a3987e8_802e8e38;
defparam bootram.RAM4.INIT_3B=256'h5452ccbb_90555351_ec0c80ee_337080f3_80eed011_83067207_088a2c70_2a8c0680;
defparam bootram.RAM4.INIT_3C=256'h0c74822e_7480f3e4_082e9838_7480f3e4_52ccd43f_dc110852_8c0680f0_3f71822b;
defparam bootram.RAM4.INIT_3D=256'h2e8e3873_80f3e808_06963873_822e0981_3f9e3974_a338feb9_2e098106_a6387481;
defparam bootram.RAM4.INIT_3E=256'h0851c9cc_c7f63f80_04fd3d0d_3f863d0d_9951c9f7_51fde83f_fe9f3f73_80f3e80c;
defparam bootram.RAM4.INIT_3F=256'h529c51c9_3f81ae80_9851ca80_d63f8d52_0c9951c9_0b80f3e8_f3e40cff_3f800b80;
defparam bootram.RAM5.INIT_00=256'h51c9d93f_70535484_07f49f06_80089080_51c9b83f_d2fc3f84_89528451_f73f80ce;
defparam bootram.RAM5.INIT_01=256'h80088480_51c98c3f_d5ea3f80_80eea851_08537352_2e8d3880_3f738008_8451c9a3;
defparam bootram.RAM5.INIT_02=256'h0a075956_0a0681d0_0a077ed0_0a0681d0_3d0d7cd0_3d0d04f6_c9b23f85_07528051;
defparam bootram.RAM5.INIT_03=256'h0c8a51cf_81ab9977_51cffd3f_71770c8a_51d0853f_710c578a_82c08072_83ffff52;
defparam bootram.RAM5.INIT_04=256'h7583ffff_51cfd93f_86770c78_805a8199_e73f80e1_0c7851cf_82d4e677_f33f8a59;
defparam bootram.RAM5.INIT_05=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_0670852a_067081ff;
defparam bootram.RAM5.INIT_06=256'h73730707_70818006_872b6306_80c00677_0676852b_077081ff_06717307_74832ba0;
defparam bootram.RAM5.INIT_07=256'h90067483_07077310_88067173_0672812a_71832a84_71872a07_852a8206_7a882a70;
defparam bootram.RAM5.INIT_08=256'h07077088_80067373_6d067081_0677872b_852b80c0_81ff0676_73070770_2ba00671;
defparam bootram.RAM5.INIT_09=256'h5752575d_58525351_5a555b51_53515752_586b4452_6d0c5151_83ffff06_2b7b0770;
defparam bootram.RAM5.INIT_0A=256'h70730770_7081ff06_0676902a_902a9680_cea63f75_770c7851_3f819981_5653ceb0;
defparam bootram.RAM5.INIT_0B=256'h90067483_07077310_88067173_0672812a_71832a84_71872a07_852a8206_81ff0670;
defparam bootram.RAM5.INIT_0C=256'h7a882a70_7081ff06_78872b07_06707207_852b80c0_81ff0676_73070770_2ba00671;
defparam bootram.RAM5.INIT_0D=256'h67405b51_680c5156_80067407_882b83fe_872b0770_06710772_852b80c0_10900671;
defparam bootram.RAM5.INIT_0E=256'h973f7783_0c7851cd_81998577_81a18056_52cda53f_57515157_58525a5a_51555351;
defparam bootram.RAM5.INIT_0F=256'h07077310_88067173_0672812a_71832a84_71872a07_852a8206_81ff0670_ffff0670;
defparam bootram.RAM5.INIT_10=256'h80067373_7f067081_0677872b_852b80c0_81ff0676_73070770_2ba00671_90067483;
defparam bootram.RAM5.INIT_11=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_2a70852a_07077a88;
defparam bootram.RAM5.INIT_12=256'h73730707_70818006_872b6906_80c00677_0676852b_077081ff_06717307_74832ba0;
defparam bootram.RAM5.INIT_13=256'h53515752_5b515852_57525a55_44525351_5151586b_ff066d0c_077083ff_70882b7b;
defparam bootram.RAM5.INIT_14=256'h902a7081_96800678_3f77902a_7851cbe0_9983770c_c1805581_cbee3f81_575c5653;
defparam bootram.RAM5.INIT_15=256'h71730707_812a8806_2a840672_2a077183_82067187_0670852a_077081ff_ff067073;
defparam bootram.RAM5.INIT_16=256'h70818006_872b6106_80c00677_0676852b_077081ff_06717307_74832ba0_73109006;
defparam bootram.RAM5.INIT_17=256'h2b750770_07077088_66067173_0672872b_852b80c0_10900671_7a882a70_73730707;
defparam bootram.RAM5.INIT_18=256'hd73f9985_515952ca_5a5b5751_53515852_5b515852_69425a54_6a0c5152_83ffff06;
defparam bootram.RAM5.INIT_19=256'h0c7851ca_3f80f077_7851cabc_3f71770c_7851cac4_3f80770c_5252cacc_70780c79;
defparam bootram.RAM5.INIT_1A=256'h3f71770c_7851ca98_3f71770c_7851caa0_3f71770c_5252caa8_70780c79_b33f8880;
defparam bootram.RAM5.INIT_1B=256'h863d2280_ffbec03f_5280d051_fc055380_8254873d_04fb3d0d_3f8c3d0d_7851ca90;
defparam bootram.RAM5.INIT_1C=256'h38775382_82932690_58595777_08841208_0880d73d_0d80d53d_04ffb23d_0c873d0d;
defparam bootram.RAM5.INIT_1D=256'h05567508_2980efac_a2387584_75962681_ff9f1656_3f81ac39_e051cef8_945280ee;
defparam bootram.RAM5.INIT_1E=256'h5c80fa39_085f80c6_f1df3f80_3f80085e_8c39f1db_08085e81_c0ea3f80_0480c15c;
defparam bootram.RAM5.INIT_1F=256'hef883f80_80f49451_8c170852_90170853_5c80ea39_065e80d6_0883ffff_ff873f80;
defparam bootram.RAM5.INIT_20=256'h80c25cb9_c45cbe39_2e863880_06567580_800881ff_51efcd3f_3980f494_c55c80d5;
defparam bootram.RAM5.INIT_21=256'h1708528c_80055390_80d03dfe_d75ca639_edef3f80_8c170851_90170852_39941753;
defparam bootram.RAM5.INIT_22=256'h80d03dfd_5c829455_3f8339a0_8051f7f7_d35c8052_5c8f3980_fb3f80d2_170851f0;
defparam bootram.RAM5.INIT_23=256'hec388380_58887826_77348118_57577533_d23d7905_58771980_0b833d5a_ec055480;
defparam bootram.RAM5.INIT_24=256'h88050851_08528c08_8c088c05_3d0d8053_028c0cfd_0d048c08_3f80d03d_8251d69b;
defparam bootram.RAM5.INIT_25=256'h0508528c_538c088c_fd3d0d81_08028c0c_8c0c048c_54853d0d_0870800c_82de3f80;
defparam bootram.RAM5.INIT_26=256'h800b8c08_0cf93d0d_8c08028c_0d8c0c04_0c54853d_80087080_5182b93f_08880508;
defparam bootram.RAM5.INIT_27=256'h050c8c08_0b8c08f4_88050c80_08308c08_8c088805_8025ab38_08880508_fc050c8c;
defparam bootram.RAM5.INIT_28=256'h25ab388c_8c050880_050c8c08_088c08fc_8c08f405_08f4050c_38810b8c_fc050888;
defparam bootram.RAM5.INIT_29=256'hf0050c8c_810b8c08_05088838_0c8c08fc_8c08f005_050c800b_308c088c_088c0508;
defparam bootram.RAM5.INIT_2A=256'h708c08f8_a73f8008_05085181_528c0888_088c0508_0c80538c_8c08fc05_08f00508;
defparam bootram.RAM5.INIT_2B=256'h70800c54_08f80508_f8050c8c_08308c08_8c08f805_802e8c38_08fc0508_050c548c;
defparam bootram.RAM5.INIT_2C=256'h93388c08_05088025_0c8c0888_8c08fc05_3d0d800b_028c0cfb_0c048c08_893d0d8c;
defparam bootram.RAM5.INIT_2D=256'h0508308c_388c088c_0880258c_8c088c05_08fc050c_0c810b8c_8c088805_88050830;
defparam bootram.RAM5.INIT_2E=256'h548c08fc_08f8050c_8008708c_0851ad3f_8c088805_8c050852_81538c08_088c050c;
defparam bootram.RAM5.INIT_2F=256'h0d8c0c04_0c54873d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e;
defparam bootram.RAM5.INIT_30=256'h08880508_8c05088c_050c8c08_0b8c08f8_fc050c80_810b8c08_0cfd3d0d_8c08028c;
defparam bootram.RAM5.INIT_31=256'h8c088c05_8c050810_99388c08_8c050824_800b8c08_802ea338_08fc0508_27ac388c;
defparam bootram.RAM5.INIT_32=256'h088c0888_8c088c05_2e80c938_fc050880_c9398c08_08fc050c_0508108c_0c8c08fc;
defparam bootram.RAM5.INIT_33=256'hfc050807_05088c08_0c8c08f8_8c088805_8c050831_05088c08_388c0888_050826a1;
defparam bootram.RAM5.INIT_34=256'h0cffaf39_8c088c05_0508812a_0c8c088c_8c08fc05_0508812a_0c8c08fc_8c08f805;
defparam bootram.RAM5.INIT_35=256'h708c08f4_08f80508_518d398c_08f4050c_0508708c_388c0888_08802e8f_8c089005;
defparam bootram.RAM5.INIT_36=256'h8c387474_52837227_77795656_fc3d0d78_0d8c0c04_800c853d_08f40508_050c518c;
defparam bootram.RAM5.INIT_37=256'h06bd3881_712e0981_33525372_38743374_71ff2ea0_38ff1252_70802eb0_07830651;
defparam bootram.RAM5.INIT_38=256'h70087308_74745451_863d0d04_800b800c_8106e238_71ff2e09_14545555_158115ff;
defparam bootram.RAM5.INIT_39=256'h7131800c_ffaf3972_70735555_8326e938_54545171_8414fc14_8f388411_2e098106;
defparam bootram.RAM5.INIT_3A=256'h2ea738ff_06517080_72750783_72278c38_5555558f_70797b55_fc3d0d76_863d0d04;
defparam bootram.RAM5.INIT_3B=256'hea387480_2e098106_125271ff_055634ff_33747081_70810554_2e983872_125271ff;
defparam bootram.RAM5.INIT_3C=256'h05530c72_08717084_70840554_05530c72_08717084_70840554_04745172_0c863d0d;
defparam bootram.RAM5.INIT_3D=256'h26c93883_1252718f_05530cf0_08717084_70840554_05530c72_08717084_70840554;
defparam bootram.RAM5.INIT_3E=256'h39fc3d0d_7054ff83_8326ed38_fc125271_8405530c_54087170_72708405_72279538;
defparam bootram.RAM5.INIT_3F=256'h125271ff_2ea238ff_06517080_8a387483_55837227_33575553_8c059f05_76797102;
defparam bootram.RAM6.INIT_00=256'h7474882b_863d0d04_3874800c_098106ef_5271ff2e_5534ff12_73708105_2e933873;
defparam bootram.RAM6.INIT_01=256'h0c727170_70840553_530c7271_71708405_27a53872_54518f72_902b0751_75077071;
defparam bootram.RAM6.INIT_02=256'h05530cfc_72717084_72279038_26dd3883_1252718f_05530cf0_72717084_8405530c;
defparam bootram.RAM6.INIT_03=256'h38717407_802e80d9_55555272_7a7c7054_fa3d0d78_53ff9039_26f23870_12527183;
defparam bootram.RAM6.INIT_04=256'h06a93872_712e0981_33565174_38713374_72ff2eb1_38ff1353_802e80d4_83065170;
defparam bootram.RAM6.INIT_05=256'h098106d1_5272ff2e_ff155555_81128115_2e80fc38_06517080_387081ff_802e8187;
defparam bootram.RAM6.INIT_06=256'h71745755_883d0d04_5270800c_71315152_81ff0671_81ff0675_33565170_38713374;
defparam bootram.RAM6.INIT_07=256'h087009f7_2eb13874_13537280_ff9739fc_74765552_082e8838_38710874_83732788;
defparam bootram.RAM6.INIT_08=256'h38740876_837327d0_84175755_9a388415_51515170_82818006_0670f884_fbfdff12;
defparam bootram.RAM6.INIT_09=256'h54547281_80f0a808_3d0d800b_3d0d04fd_0b800c88_fedf3980_74765552_082ed038;
defparam bootram.RAM6.INIT_0A=256'h51ffb7ca_d53f8008_8151ffad_80f0ec52_ffa5b13f_ffa6953f_80f3f00c_2e9f3873;
defparam bootram.RAM6.INIT_0B=256'hb7ac3f00_800851ff_ffadb73f_ec528151_933f80f0_f73fffa5_f00cffa5_3f7280f3;
defparam bootram.RAM6.INIT_0C=256'h70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570_0d80f0f4_ff39ff3d;
defparam bootram.RAM6.INIT_0D=256'h20612063_69766564_52656365_00000040_3f040000_04ffa6a1_833d0d04_8106f138;
defparam bootram.RAM6.INIT_0E=256'h6c697479_74696269_6f6d7061_74682063_74207769_61636b65_6f6c2070_6f6e7472;
defparam bootram.RAM6.INIT_0F=256'h7220636f_68206f75_20776974_79696e67_5265706c_25642e20_62657220_206e756d;
defparam bootram.RAM6.INIT_10=256'h69766564_52656365_642e0a00_65722025_6e756d62_69747920_6962696c_6d706174;
defparam bootram.RAM6.INIT_11=256'h796c6f61_64207061_65637465_20457870_6b65743a_20706163_686f7274_20612073;
defparam bootram.RAM6.INIT_12=256'h64696e67_2053656e_2025642e_20676f74_20627574_2025642c_6e677468_64206c65;
defparam bootram.RAM6.INIT_13=256'h0a657468_00000000_4841540a_55485f57_49445f48_54524c5f_50325f43_20555352;
defparam bootram.RAM6.INIT_14=256'h0a556d54_640a0000_203d2025_70656564_643a2073_616e6765_6b206368_206c696e;
defparam bootram.RAM6.INIT_15=256'h62696c69_70617469_20636f6d_46504741_720a0000_6f616465_6f6f746c_52582062;
defparam bootram.RAM6.INIT_16=256'h2e25642d_3a202564_77617265_4669726d_640a0000_723a2025_756d6265_7479206e;
defparam bootram.RAM6.INIT_17=256'h476f7420_00000000_61646472_00000000_646f6e65_20697320_496e6974_25780a00;
defparam bootram.RAM6.INIT_18=256'h00000713_0000072a_00000000_65743a20_7061636b_65727920_65636f76_69702072;
defparam bootram.RAM6.INIT_19=256'h000007c3_000007c3_000007c3_000007c3_000007c3_00000799_000007c3_000007c3;
defparam bootram.RAM6.INIT_1A=256'h000007c3_000007c3_000007c3_000007c3_0000066d_000007c3_000006db_00000747;
defparam bootram.RAM6.INIT_1B=256'h000006d2_000006cd_000006c8_000006c3_000006ac_000006a2_00000695_0000067a;
defparam bootram.RAM6.INIT_1C=256'h20636869_4c4d5331_00000787_0000077a_00000773_0000076c_00000767_00000762;
defparam bootram.RAM6.INIT_1D=256'h70207665_20636869_4c4d5332_0a000000_30782578_6e203d20_7273696f_70207665;
defparam bootram.RAM6.INIT_1E=256'h4661696c_00000000_6f72740a_0a0a6162_0a000000_30782578_6e203d20_7273696f;
defparam bootram.RAM6.INIT_1F=256'hc0a80a02_67000000_20666c61_626f6f74_61666520_61642073_6f207265_65642074;
defparam bootram.RAM6.INIT_20=256'h38394142_34353637_30313233_01c300e2_054a0387_15290a94_3fff0000_0050c285;
defparam bootram.RAM6.INIT_21=256'h38394142_34353637_30313233_2e256400_642e2564_25642e25_45000000_43444546;
defparam bootram.RAM6.INIT_22=256'h6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546;
defparam bootram.RAM6.INIT_23=256'h6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d;
defparam bootram.RAM6.INIT_24=256'h6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d;
defparam bootram.RAM6.INIT_25=256'h72642073_20776569_6172703a_646c655f_0a68616e_00000000_666f7220_696e6720;
defparam bootram.RAM6.INIT_26=256'h206c656e_74656e74_6e736973_696e636f_55445020_0a000000_3d202564_697a6520;
defparam bootram.RAM6.INIT_27=256'h20000000_3a202564_20444143_5443584f_00000000_2025640a_3a202564_67746873;
defparam bootram.RAM6.INIT_28=256'h0a666c61_64210000_61696c65_4f472066_54434844_74205741_5f776169_73706966;
defparam bootram.RAM6.INIT_29=256'h6c617368_6e672066_0a57726f_25640a00_697a653d_25642073_7970653d_73682074;
defparam bootram.RAM6.INIT_2A=256'h6c617368_6e672066_0a57726f_00000000_6e67210a_63687475_652e2041_20747970;
defparam bootram.RAM6.INIT_2B=256'h53504920_0b0b0000_10101200_67210a00_6874756e_64204163_653a2025_2073697a;
defparam bootram.RAM6.INIT_2C=256'h50726f64_65640000_616c697a_6e697469_656e2069_73206265_68206861_466c6173;
defparam bootram.RAM6.INIT_2D=256'h20556d54_74696e67_53746172_640a0000_203d2025_6d616765_6f6e2069_75637469;
defparam bootram.RAM6.INIT_2E=256'h20666f72_6b696e67_43686563_00000000_6f64652e_6665206d_6e207361_52582069;
defparam bootram.RAM6.INIT_2F=256'h2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070_2076616c;
defparam bootram.RAM6.INIT_30=256'h666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072_56616c69;
defparam bootram.RAM6.INIT_31=256'h64756374_2070726f_616c6964_4e6f2076_00000000_6e672e2e_6f6f7469_642c2062;
defparam bootram.RAM6.INIT_32=256'h64207072_56616c69_2e0a0000_6f756e64_67652066_20696d61_46504741_696f6e20;
defparam bootram.RAM6.INIT_33=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563;
defparam bootram.RAM6.INIT_34=256'h523a2052_4552524f_2e000000_67652e2e_20696d61_74696e67_53746172_2e2e2e00;
defparam bootram.RAM6.INIT_35=256'h2070726f_616c6964_4e6f2076_00000000_61696e21_6f6d206d_6e206672_65747572;
defparam bootram.RAM6.INIT_36=256'h64207365_53706565_6e642100_20666f75_77617265_6669726d_696f6e20_64756374;
defparam bootram.RAM6.INIT_37=256'h57455f52_58000000_57455f54_00000000_4e4f4e45_00000000_2025640a_7420746f;
defparam bootram.RAM6.INIT_38=256'h7720636f_20666c6f_726e6574_65746865_43000000_45545249_53594d4d_58000000;
defparam bootram.RAM6.INIT_39=256'h74652030_2077726f_4144563a_4e45475f_4155544f_5048595f_6c3a2000_6e74726f;
defparam bootram.RAM6.INIT_3A=256'h00030203_00000001_00030003_00000000_780a0000_20307825_20676f74_7825782c;
defparam bootram.RAM6.INIT_3B=256'h6c65723a_68616e64_6b657420_20706163_64617465_6e207570_6f722069_21457272;
defparam bootram.RAM6.INIT_3C=256'h20627574_2025642c_6e677468_64206c65_796c6f61_64207061_65637465_20457870;
defparam bootram.RAM6.INIT_3D=256'h00002bf0_00002c05_00002c57_00002c57_00002bc1_00000000_2025640a_20676f74;
defparam bootram.RAM6.INIT_3E=256'h00002c57_00002c57_00002c57_00002c57_00002c57_00002c57_00002c57_00002bce;
defparam bootram.RAM6.INIT_3F=256'h00002c57_00002c57_00002c4b_00002c34_00002c57_00002c57_00002c57_00002c57;
defparam bootram.RAM7.INIT_00=256'hffff00ff_ff00ffff_00ffffff_65000000_792e6578_64756d6d_00002c21_00002be0;
defparam bootram.RAM7.INIT_01=256'h3fff0000_0050c285_c0a80a02_0000387c_00000000_00000000_00000000_ffffff00;
defparam bootram.RAM7.INIT_02=256'h000036ec_02000000_18cba800_000c0000_00190010_ffff0033_04000400_01010100;
defparam bootram.RAM7.INIT_03=256'h00000000_ffffffff_00000000_ffffffff_00003808_00003704_000036fc_000036f4;
defparam bootram.RAM0.INIT_30=256'h5a588379_84120859_3d0d686a_3d0d04ee_9aaa3f94_7c26ef38_811c5c86_79337b34;
defparam bootram.RAM0.INIT_31=256'hf55778a3_95983f80_80e0c851_75538c52_802e8c38_2e943875_0856758c_279c3877;
defparam bootram.RAM0.INIT_32=256'h75922682_ff981756_8818085d_8c5ba05c_853fa057_e1985195_53a45280_268e3878;
defparam bootram.RAM0.INIT_33=256'h5c8c1808_983980da_08085e82_88b73f80_0480d55c_05567508_2980e388_ae387584;
defparam bootram.RAM0.INIT_34=256'h39921822_065f81f5_0883ffff_abd63f80_38828239_75822e91_812e8938_5e7d5675;
defparam bootram.RAM0.INIT_35=256'h1808538c_18335490_57765596_2e833884_577580f2_18335682_81eb3995_51aba43f;
defparam bootram.RAM0.INIT_36=256'h81b3398d_5f80d35c_933f8008_57765196_2e833881_57577577_0b971933_18085280;
defparam bootram.RAM0.INIT_37=256'h19538c19_3370548e_94398d18_3f80c95c_52568bca_538c1933_953dea05_18337054;
defparam bootram.RAM0.INIT_38=256'h80c23875_56758526_1833ff05_80ff3994_05b50534_5c750284_983f80c8_3352568d;
defparam bootram.RAM0.INIT_39=256'h0ca23992_90180877_225fa939_5fae3976_08047608_08585675_d4058c19_842980e3;
defparam bootram.RAM0.INIT_3A=256'h08710c56_a0059019_842980ef_568e3976_05700840_2980efa0_9b397684_18227723;
defparam bootram.RAM0.INIT_3B=256'h3d790557_58771996_0b833d5a_dc055480_0855943d_cc5c8c18_39785e80_80d25cad;
defparam bootram.RAM0.INIT_3C=256'h5a587719_800b833d_3ddc0554_5ca45594_38a439a0_887826ed_34811858_57753377;
defparam bootram.RAM0.INIT_3D=256'h04fd3d0d_3f943d0d_80519b99_ed388380_58887826_77348118_57577533_963d7905;
defparam bootram.RAM0.INIT_3E=256'h52725186_80c05372_e82e8438_a0537387_802e9838_92883f73_e1e45254_75705380;
defparam bootram.RAM0.INIT_3F=256'h0d82903f_0d04fa3d_b03f853d_52735186_b83f80c0_52735186_3f9039a0_c43f9ba6;
defparam bootram.RAM1.INIT_00=256'hefbc0cf9_3f820b80_c05191ba_8c5280e2_5191c33f_5280e2a0_87a93f89_80e28451;
defparam bootram.RAM1.INIT_01=256'h9c0c82d6_800b81e0_81e09c0c_e93f810b_84803f84_0cabdf3f_0b80efb8_cd909299;
defparam bootram.RAM1.INIT_02=256'h80085483_3f84ce3f_f63f869e_8008518f_3f84da3f_dc3f86aa_8008518f_3f84863f;
defparam bootram.RAM1.INIT_03=256'h52838080_ac3f8c93_8def3f94_52800851_3f838084_a23f84bd_80085194_e83f7352;
defparam bootram.RAM1.INIT_04=256'h51a5843f_3f838092_825194d3_a8528380_de3f80c7_80845194_8ab25283_5194e83f;
defparam bootram.RAM1.INIT_05=256'hc9387680_08802e80_80085680_518dea3f_883dfc05_3faecf3f_bd51acaa_8dda3f8f;
defparam bootram.RAM1.INIT_06=256'hcca63f80_90055180_e4528008_845380e2_8106ad38_fdee2e09_55557382_088e0522;
defparam bootram.RAM1.INIT_07=256'h74527551_fd3f8839_3f735183_da3f8582_7052548e_e93f9416_e2ec518f_089a3880;
defparam bootram.RAM1.INIT_08=256'ha13f86f2_85f63f8b_3f91b13f_3d0d84cb_ff9e39fe_3f8be93f_f73fa4d9_9a8d3f8c;
defparam bootram.RAM1.INIT_09=256'h82ac518a_5183ea3f_3f845284_ac518ae0_83f73f82_9f528051_51849b3f_3f9f5280;
defparam bootram.RAM1.INIT_0A=256'h82539f52_518ab93f_d03f82ac_52905183_8ac63f90_3f82ac51_885183dd_d33f8852;
defparam bootram.RAM1.INIT_0B=256'h8025df38_ff135372_518a9d3f_b43f80e4_529c5183_8aaa3f9f_3f80e451_805183c1;
defparam bootram.RAM1.INIT_0C=256'h5683760c_0d81e080_0d04fb3d_800c843d_983f810b_52815183_83bc3f9f_9f529e51;
defparam bootram.RAM1.INIT_0D=256'h5190a93f_53815281_90548880_760c8655_89e63f83_0c80e451_ef3f8076_80e45189;
defparam bootram.RAM1.INIT_0E=256'he488518d_80085280_5190913f_53825281_90548880_893f8655_e3ec518e_80085280;
defparam bootram.RAM1.INIT_0F=256'h279e3872_80537276_81705654_787a5757_04fa3d0d_0c873d0d_3f810b80_f13fa6e1;
defparam bootram.RAM1.INIT_10=256'h74740751_1353df39_38805581_81ff2e83_71335271_83388054_5270802e_17703352;
defparam bootram.RAM1.INIT_11=256'h5280eec4_5380e4a8_efc43486_0d810b80_0d04fe3d_800c883d_38815170_70802e83;
defparam bootram.RAM1.INIT_12=256'h873d7054_c4348654_810b80ef_5574bd38_80efc433_04f93d0d_3f843d0d_5180c798;
defparam bootram.RAM1.INIT_13=256'h0881ff06_fef33f80_86527551_802e9d38_ff065574_3f800881_d051b5d0_56825280;
defparam bootram.RAM1.INIT_14=256'h80efc034_0d04810b_800c893d_80eec40b_80c6cd3f_80eec451_86537552_55748d38;
defparam bootram.RAM1.INIT_15=256'h873dfc05_c0348454_810b80ef_5574b938_80efc033_04fb3d0d_80eec00c_80e4a408;
defparam bootram.RAM1.INIT_16=256'h903f8008_fc0551fe_8452873d_802e9938_ff065574_3f800881_d051b4f0_538c5280;
defparam bootram.RAM1.INIT_17=256'h5475538c_0d775684_0d04fb3d_800c873d_80eec00b_80eec00c_74863875_81ff0655;
defparam bootram.RAM1.INIT_18=256'hc0347480_810b80ef_80eec00c_8d387508_5574802e_0881ff06_b3b63f80_5280d051;
defparam bootram.RAM1.INIT_19=256'h0c51823d_0c81e08c_7080efc8_c8080607_067180ef_73097375_04803d0d_0c873d0d;
defparam bootram.RAM1.INIT_1A=256'h3d0d0481_980c5182_cc0c81e0_077080ef_efcc0806_75067180_0d730973_0d04803d;
defparam bootram.RAM1.INIT_1B=256'h5181b63f_0d8a5280_0d04ff3d_800c843d_81c73f72_53538051_3d0d7470_af3f04fe;
defparam bootram.RAM1.INIT_1C=256'hff065376_81157481_802e9038_06545472_337081ff_79565674_fb3d0d77_833d0d04;
defparam bootram.RAM1.INIT_1D=256'hfe3d0d74_833d0d04_8051cd3f_3d0d7352_3d0d04ff_0b800c87_3fe53980_52558191;
defparam bootram.RAM1.INIT_1E=256'h8051dd3f_3d0d7352_3d0d04ff_0b800c84_80e73f80_8a527251_53ffbd3f_76537052;
defparam bootram.RAM1.INIT_1F=256'h82908005_0d73a029_0d04ff3d_1234823d_3380eecc_51028f05_803d0d72_833d0d04;
defparam bootram.RAM1.INIT_20=256'h51c63f80_13335272_5380eecc_fe3d0d80_833d0d04_720c5351_b0057022_751080e4;
defparam bootram.RAM1.INIT_21=256'h748a2e09_76785654_04fc3d0d_38843d0d_827325e5_3f811353_527251ce_eed01333;
defparam bootram.RAM1.INIT_22=256'h90800554_73a02982_7351de3f_87388d52_2e098106_33537281_80eecc14_81069538;
defparam bootram.RAM1.INIT_23=256'h11085252_90800588_74a02982_04fe3d0d_0c863d0d_38748c15_72802ef8_84140853;
defparam bootram.RAM1.INIT_24=256'heed82270_a8880c80_0d800b81_0d04ff3d_800c843d_12085372_2e853890_ff537080;
defparam bootram.RAM1.INIT_25=256'h0d787a02_0d04fb3d_880c833d_800b81a8_840c5181_882a81a8_a8800c70_81ff0681;
defparam bootram.RAM1.INIT_26=256'h81065151_70862a70_81a89008_8386d053_2e81c738_81527380_33575556_88059f05;
defparam bootram.RAM1.INIT_27=256'h81a88c0c_74108107_52819f39_fde53f72_80e4bc51_5372e938_9338ff13_5271802e;
defparam bootram.RAM1.INIT_28=256'h38ff1353_71802e8e_06515152_812a7081_a8900870_86d05381_a8900c83_81900b81;
defparam bootram.RAM1.INIT_29=256'h802e80cf_51515271_70813251_2a708106_90087087_ae3f81a8_e4d851fd_72e93880;
defparam bootram.RAM1.INIT_2A=256'h90087081_d05381a8_900c8386_527181a8_2e8338a0_e8527381_80c53880_3873802e;
defparam bootram.RAM1.INIT_2B=256'h08527176_3f81a88c_d851fcdf_e93880e4_ff135372_802e8e38_51515271_2a708106;
defparam bootram.RAM1.INIT_2C=256'h04fb3d0d_0c873d0d_900c7180_c00b81a8_52883980_ffb73981_34ff1454_70810558;
defparam bootram.RAM1.INIT_2D=256'h71802e93_06515152_862a7081_a8900870_86d05381_57555683_059f0533_787a0288;
defparam bootram.RAM1.INIT_2E=256'h73802e84_0c81d052_1081a88c_81bb3974_8a3f7252_e4f851fc_72e93880_38ff1353;
defparam bootram.RAM1.INIT_2F=256'h2e8e38ff_51527180_70810651_0870812a_5381a890_0c8386d0_7181a890_38819052;
defparam bootram.RAM1.INIT_30=256'h5271802e_32515151_81067081_70872a70_81a89008_51fbcc3f_3880e4d8_135372e9;
defparam bootram.RAM1.INIT_31=256'h900c8386_527181a8_2e833890_d0527381_a88c0c80_38753381_802e80d8_80e23873;
defparam bootram.RAM1.INIT_32=256'hd851faf7_e93880e4_ff135372_802e8e38_51515271_2a708106_90087081_d05381a8;
defparam bootram.RAM1.INIT_33=256'h56ffa439_16ff1555_2e8e3881_51527180_81325151_70810670_0870872a_3f81a890;
defparam bootram.RAM1.INIT_34=256'h74259b38_54805372_fd3d0d75_873d0d04_5271800c_a8900c80_80c00b81_81528a39;
defparam bootram.RAM1.INIT_35=256'h0d04ff3d_e239853d_38811353_8f7127f1_515181cb_08707331_5281b8ac_81b8ac08;
defparam bootram.RAM1.INIT_36=256'h8c528751_8c0c80fa_ff0b8280_8280840c_800cef0b_e00b8280_80880c81_0dff0b82;
defparam bootram.RAM1.INIT_37=256'h0982808c_80880870_fb3d0d82_833d0d04_8025f138_ff115170_8405540c_9ee47270;
defparam bootram.RAM1.INIT_38=256'h52712d74_72517308_802e8f38_76065271_8c555574_810b80fa_51528053_08710658;
defparam bootram.RAM1.INIT_39=256'h52718726_ff3d0d73_873d0d04_7325dc38_57555387_84157610_8f398113_82808c0c;
defparam bootram.RAM1.INIT_3A=256'h0c535152_06828088_88087072_70098280_5181722b_0575710c_2980fa8c_9f387184;
defparam bootram.RAM1.INIT_3B=256'h803d0d81_833d0d04_81e0c80c_e0c40c52_74700881_02920522_04ff3d0d_833d0d04;
defparam bootram.RAM1.INIT_3C=256'h04fe3d0d_0c823d0d_0b81e0c0_2ef33882_51517080_08708406_0c81b8a0_0b81e0c0;
defparam bootram.RAM1.INIT_3D=256'h80529a39_53538180_902a710c_a0087571_933881b8_5272802e_70810654_81b8a008;
defparam bootram.RAM1.INIT_3E=256'h843d0d04_5271800c_ffa63f72_51f7dc3f_3880e594_71802e8b_81065152_71812a70;
defparam bootram.RAM1.INIT_3F=256'hff3d0d02_823d0d04_800b800c_f2388180_5170802e_80c00651_b8a00870_803d0d81;
defparam bootram.RAM2.INIT_00=256'h0b81e0c0_2ef33884_51517080_08709006_5281b8a0_81e0c00c_902b8807_8e052270;
defparam bootram.RAM2.INIT_01=256'haccd3f81_70335252_ae3f7214_38ba51f6_72802e86_75548053_04fd3d0d_0c833d0d;
defparam bootram.RAM2.INIT_02=256'h33535680_11335470_11335581_11335682_3d0d7783_3d0d04fb_27e63885_13538573;
defparam bootram.RAM2.INIT_03=256'h515b5f5d_30709f2a_bb053370_63029005_0d7c7e61_0d04f63d_ed3f873d_e5985180;
defparam bootram.RAM2.INIT_04=256'h55785480_26943879_30577777_51782d76_387952ad_75802e8a_80258f38_5b595776;
defparam bootram.RAM2.INIT_05=256'h51782d8c_e5a40533_3f800880_7651b593_bd3f7752_800851ff_51b4fb3f_53775276;
defparam bootram.RAM2.INIT_06=256'h08a1c35c_70840552_0d8c3d70_0d04f73d_963f823d_053351f5_3d0d028b_3d0d0480;
defparam bootram.RAM2.INIT_07=256'hdb388119_09810680_5675a52e_7681ff06_2e81d138_57577580_7081ff06_5a587833;
defparam bootram.RAM2.INIT_08=256'h3875802e_80e3248a_2eb93875_387580e3_80f024a0_80fb3875_7580f02e_70335759;
defparam bootram.RAM2.INIT_09=256'h7580f32e_f5248b38_ac387580_7580f52e_38818b39_e42e80c6_95397580_819e3881;
defparam bootram.RAM2.INIT_0A=256'h792d80da_80527551_33525956_84198312_80ec3977_f82eba38_f5397580_80db3880;
defparam bootram.RAM2.INIT_0B=256'ha1c35481_59568055_19710852_90397784_c3548053_568055a1_71085259_39778419;
defparam bootram.RAM2.INIT_0C=256'h39778419_fdd03f9e_90527551_c3548053_568055a1_71085259_39778419_538a5292;
defparam bootram.RAM2.INIT_0D=256'h59fea339_ec398119_3351792d_70810558_38805276_75802e8e_56763356_71085959;
defparam bootram.RAM2.INIT_0E=256'h81065151_2a813270_b408708c_3d0d81b8_e40c0480_8a0b81e5_8b3d0d04_800b800c;
defparam bootram.RAM2.INIT_0F=256'h55575454_72810655_982b7b07_9b053372_7b028805_fc3d0d79_823d0d04_5170ef38;
defparam bootram.RAM2.INIT_10=256'ha0743179_820a0752_2e863871_51517080_2a708106_07527282_3871810a_70802e86;
defparam bootram.RAM2.INIT_11=256'h742bff05_ff953f81_802e9338_0c745174_7081e5ec_81e5e80c_ffa93f71_712b5151;
defparam bootram.RAM2.INIT_12=256'h7274278f_55558053_76787a54_04fc3d0d_0c863d0d_52527080_70720651_81b88008;
defparam bootram.RAM2.INIT_13=256'h0672902a_7183ffff_802e8d38_902a5170_51ee3971_81155553_70227305_38721015;
defparam bootram.RAM2.INIT_14=256'h80efdc0c_3f767008_d451b6c4_755280ef_3d0d8653_3d0d04fd_71800c86_0552ec39;
defparam bootram.RAM2.INIT_15=256'h833d0d04_8025f338_12525270_0c8812ff_89518072_80efe452_04ff3d0d_54853d0d;
defparam bootram.RAM2.INIT_16=256'h52897225_12881252_2e8e3881_22547274_e0525270_800b80ef_96052253_fd3d0d02;
defparam bootram.RAM2.INIT_17=256'h802e8938_c73f8008_06535856_7183ffff_3d0d787a_3d0d04fa_70800c85_ee388051;
defparam bootram.RAM2.INIT_18=256'h2e8f3881_55527180_73088815_e0555555_e40b80ef_800880ef_050cad39_76800884;
defparam bootram.RAM2.INIT_19=256'h7054933d_f13d0d86_883d0d04_7684140c_3f757323_eb38a381_55897525_15881454;
defparam bootram.RAM2.INIT_1A=256'h8405a205_3f908002_0551b584_52913ddc_923d8805_933f7353_055254b5_53923dd6;
defparam bootram.RAM2.INIT_1B=256'h2380c091_8405aa05_81808002_0b8c3d23_a6052380_80028405_0b8b3d23_23818a80;
defparam bootram.RAM2.INIT_1C=256'h08028405_fdb73f80_3de40551_538a5291_5d665e80_ae052368_80028405_0b8d3d23;
defparam bootram.RAM2.INIT_1D=256'h0523ac53_028405be_913d2380_0523800b_028405ba_23963d22_3d22903d_ae052398;
defparam bootram.RAM2.INIT_1E=256'h973d2386_805b800b_04e83d0d_3f913d0d_0551a4f4_29829884_526980c0_913dd405;
defparam bootram.RAM2.INIT_1F=256'hf2052202_e33f0280_f80551b3_d4529a3d_865380ef_51b3f13f_9a3df205_539b3d52;
defparam bootram.RAM2.INIT_20=256'h3d0845a3_436e44a1_1143f005_0b9b3dc4_08585a80_3f800880_0523f7d8_840580e2;
defparam bootram.RAM2.INIT_21=256'h08701a78_56845875_06408c3d_088305fc_085fa33d_6e5ea13d_845c905d_3d084659;
defparam bootram.RAM2.INIT_22=256'h0654738c_9a387383_5473802e_760c7508_27843873_5a557375_71315156_7c319080;
defparam bootram.RAM2.INIT_23=256'ha3c63f75_08527651_08539416_eee53f75_80e5c051_802e8838_83065473_38941608;
defparam bootram.RAM2.INIT_24=256'hf6de3f9a_78822a51_3880c059_78bf2684_25ffac38_59577780_0817ff19_70840557;
defparam bootram.RAM2.INIT_25=256'h0523800b_840580ca_055a7902_237f1f94_800b943d_4040818a_3d0d6b6e_3d0d04ea;
defparam bootram.RAM2.INIT_26=256'hd2052380_02840580_963d2380_80075a79_236980c0_0580ce05_80800284_953d2381;
defparam bootram.RAM2.INIT_27=256'h0523913d_840580d2_095a7902_e03f8008_70525cfa_8a52933d_68478053_efdc0846;
defparam bootram.RAM2.INIT_28=256'h51f6ac3f_f7b83f7a_80e5ec51_5a799238_0881ff06_8ac83f80_70535c5e_7053983d;
defparam bootram.RAM2.INIT_29=256'h5b5b7933_7b1d7c1f_8053805c_557b5490_6b575d94_6d596058_39027f5a_ecd43fa9;
defparam bootram.RAM2.INIT_2A=256'h238d3d22_05228a3d_7f5802ae_04f73d0d_3f983d0d_ef38fd89_5c867c26_7b34811c;
defparam bootram.RAM2.INIT_2B=256'hf8055391_88548b3d_77567e55_05a60523_23800284_57768b3d_05238818_028405a2;
defparam bootram.RAM2.INIT_2C=256'h8f3d3484_0523860b_028405b2_3d239080_0d810b8e_0d04ee3d_9e3f8b3d_527d51fe;
defparam bootram.RAM2.INIT_2D=256'h3fe9ea3f_0551b0a0_52943dec_86538008_23e99a3f_8405b605_05348102_028405b5;
defparam bootram.RAM2.INIT_2E=256'h80080843_3fe9ce3f_0551b19d_52943df6_3f865380_0551b090_52943df2_84538008;
defparam bootram.RAM2.INIT_2F=256'h1b337a34_5a80e5b8_805b7a1c_54908653_943de405_80569c55_80588057_025c8059;
defparam bootram.RAM2.INIT_30=256'h862e0981_5f5d7d90_088e1122_3d0daa3d_3d0d04d9_fbcb3f94_7b26ef38_811b5b86;
defparam bootram.RAM2.INIT_31=256'h3f86ee39_9c51f596_795280e6_9b268d38_055b5b79_088429f2_901dac3d_06829d38;
defparam bootram.RAM2.INIT_32=256'h225a798c_d438841b_09810686_7990802e_821b225a_0686e238_812e0981_7a225a79;
defparam bootram.RAM2.INIT_33=256'h3fa81d70_52408885_389e1d70_810686b9_79812e09_861b225a_0686c638_842e0981;
defparam bootram.RAM2.INIT_34=256'h868f38a7_085c8008_add23f80_ffa80551_dc52a93d_845380ef_3f800843_525f87fd;
defparam bootram.RAM2.INIT_35=256'h841b33a2_80fe0523_22028405_3d23821b_3f7a22a1_7951aeb0_80efd452_3d5a8653;
defparam bootram.RAM2.INIT_36=256'h51adfd3f_a93de405_86537952_81820523_82028405_81810534_33028405_3d34851b;
defparam bootram.RAM2.INIT_37=256'h3f79537f_7a51ade0_53981d52_8e055b86_ef3f0281_05525aad_53aa3dea_8470547f;
defparam bootram.RAM2.INIT_38=256'h7c575d9c_7c597c58_3f027c5a_7e51adc8_86537a52_3f9e3d5f_0551add4_52a93df4;
defparam bootram.RAM2.INIT_39=256'h3f84ee39_ef38f999_5c867c26_7b34811c_5b5b7933_7b1d7f1d_05547d53_55a93ddc;
defparam bootram.RAM2.INIT_3A=256'h3879882a_810684d1_60842e09_2a435b5b_7022708c_e438901d_09810684_7d90802e;
defparam bootram.RAM2.INIT_3B=256'h865380e5_b4387e5e_065f7e84_2280ffff_c038861b_09810684_5a79852e_708f0651;
defparam bootram.RAM2.INIT_3C=256'hcb3f8008_535b5cab_efdc5470_1c625580_815e7e90_80088338_51abe13f_b852821d;
defparam bootram.RAM2.INIT_3D=256'hec11405d_33821c22_b83f891b_9c1d5184_38881d52_802e8481_7d87387b_8338815c;
defparam bootram.RAM2.INIT_3E=256'h42407d7a_11225d5d_08a41f84_8c1b087a_0683de38_912e0981_81bb387f_407f812e;
defparam bootram.RAM2.INIT_3F=256'hc33f8008_535d5df5_1d821d22_39ac1de4_e53f83bd_e6bc51f1_537d5280_2e8f3879;
defparam bootram.RAM3.INIT_00=256'hbf3f9c3d_527951ab_5a88537d_3d993d5f_237f499a_7a22993d_2e83a638_42800880;
defparam bootram.RAM3.INIT_01=256'hab9e3f88_05527951_a93dffb4_60478853_22973d23_b33f821b_527f51ab_40885379;
defparam bootram.RAM3.INIT_02=256'h1c5c887c_337b3481_1f5b5b79_5c7b1d7c_7e843d5e_7b567c55_51ab953f_5379527d;
defparam bootram.RAM3.INIT_03=256'h792d82ad_8405085a_26ef3861_1b5b887b_051c3481_79330284_5b7f1b5a_26ef3880;
defparam bootram.RAM3.INIT_04=256'h5a79832e_39811a33_bb388295_7d882e81_832e8a38_405b427d_a41e7033_398c1b08;
defparam bootram.RAM3.INIT_05=256'h51f4813f_f4387c22_09810681_5c79912e_12335c5e_80c01e89_a238ac1d_09810681;
defparam bootram.RAM3.INIT_06=256'h537a527d_3d5c5e88_4b983d9b_9b3d2379_085a7c22_fe388c1c_08802e80_80084180;
defparam bootram.RAM3.INIT_07=256'h8853a93d_3d23794d_821d229d_901c085a_51a9ed3f_537d527f_963d4088_51a9f93f;
defparam bootram.RAM3.INIT_08=256'h7c1f5b5b_5e5c7b1d_557e843d_3f7e567e_7d51a9cc_88537a52_51a9d53f_cc05527a;
defparam bootram.RAM3.INIT_09=256'h7b26ef38_811b5b88_84051c34_5a793302_805b7f1b_7c26ef38_811c5c88_79337b34;
defparam bootram.RAM3.INIT_0A=256'h840580cd_3d347e02_5d5d7e95_ac1de41d_3f80de39_e951e497_5a792d80_60840508;
defparam bootram.RAM3.INIT_0B=256'h6052943d_05237e53_840580d2_861a2202_22963d23_0523841a_840580ce_05347e02;
defparam bootram.RAM3.INIT_0C=256'h05237b56_840580ce_095a7902_c03f8008_527c51f1_537b812a_cc3f8008_70525bf1;
defparam bootram.RAM3.INIT_0D=256'h727427a4_b0085553_800b80f0_04fc3d0d_3fa93d0d_6151f5f7_7a537f52_7c557d54;
defparam bootram.RAM3.INIT_0E=256'h81135373_72518b39_81068538_70752e09_8c135351_56517108_80f0b854_38767008;
defparam bootram.RAM3.INIT_0F=256'h25ba3880_3f800880_5755ffb9_77797153_04fb3d0d_0c863d0d_ff517080_7326e738;
defparam bootram.RAM3.INIT_10=256'h0c547310_0680f0b4_08811187_3980f0b4_f0b00c8e_38811480_73872689_f0b00854;
defparam bootram.RAM3.INIT_11=256'h08055486_80081080_14519439_5280f0bc_54865375_b8120c51_760880f0_1470822b;
defparam bootram.RAM3.INIT_12=256'h73800824_d83f8054_0d7551fe_0d04fd3d_8f3f873d_bc0551a7_842980f0_53755273;
defparam bootram.RAM3.INIT_13=256'h0c853d0d_81547380_51a6e53f_bc055276_842980f0_54865373_10800805_99388008;
defparam bootram.RAM3.INIT_14=256'h7107800c_07831633_70882b72_07821433_2b71902b_12337198_75703381_04fd3d0d;
defparam bootram.RAM3.INIT_15=256'hff068b3d_387383ff_595776a8_f1982256_0d7d7f80_0d04f93d_5452853d_52535456;
defparam bootram.RAM3.INIT_16=256'h2380c039_51547674_80f19c05_14709029_38739029_832680d3_52565473_22707231;
defparam bootram.RAM3.INIT_17=256'h52739029_88538a3d_90291554_26ad3874_57547483_70723157_068d3d22_7383ffff;
defparam bootram.RAM3.INIT_18=256'h56ec3989_9c3f8116_547451e2_17703353_27913875_80567578_51a5d53f_80f19c05;
defparam bootram.RAM3.INIT_19=256'h140c800b_800b8288_54807323_80f19c54_9823800b_052280f1_3d0d029a_3d0d04fc;
defparam bootram.RAM3.INIT_1A=256'h38863d0d_837427d9_90145454_3f811482_0551ef9b_f1982274_b5aa5280_828c140c;
defparam bootram.RAM3.INIT_1B=256'h1a085b5d_38758288_567581be_70810651_7c2c8132_9c5a5c82_800b80f1_04f43d0d;
defparam bootram.RAM3.INIT_1C=256'h06708a32_800881ff_2e80c538_3f8008ff_7b51e1e1_1a88055b_80d63878_7981ff26;
defparam bootram.RAM3.INIT_1D=256'h7b708105_38815d77_76802e83_59515858_25075351_80257180_32703072_7030728d;
defparam bootram.RAM3.INIT_1E=256'h82881908_27ffb138_5a81ff7a_1a0c811a_800b828c_82881a0c_19088105_5d348288;
defparam bootram.RAM3.INIT_1F=256'h802eab38_78225675_7627bf38_1b0c568b_8111828c_828c1908_387c9138_802e80d2;
defparam bootram.RAM3.INIT_20=256'h7826ef38_81185888_75337734_781a5757_5b58771a_800b833d_55881954_82881908;
defparam bootram.RAM3.INIT_21=256'h5c837c27_82901a5a_1a0c811c_800b828c_82881a0c_a83f800b_7c0551f2_80f19822;
defparam bootram.RAM3.INIT_22=256'h53845281_759fff06_85559054_80faac23_05225675_3d0d029e_3d0d04fb_fea9388e;
defparam bootram.RAM3.INIT_23=256'h51515372_2a708106_80087081_3d0d81b0_800c04fa_80faac22_873d0d04_51eb853f;
defparam bootram.RAM3.INIT_24=256'ha43880ee_9abe2681_1453728c_e7a0a39f_81b0800c_0854810b_3881b084_802e81bd;
defparam bootram.RAM3.INIT_25=256'h58515380_80713152_0c98e5ea_7080eee0_0570832c_31741184_80eee008_e0088829;
defparam bootram.RAM3.INIT_26=256'h902b7090_f9dc2270_b1f05380_258538ff_72ffb1f0_90538c39_873880ce_ce907325;
defparam bootram.RAM3.INIT_27=256'h2270902b_2980f9e0_70902c73_2270902b_0c80f9de_7080f9f0_f9f00816_2c752980;
defparam bootram.RAM3.INIT_28=256'h56515654_5351555b_2c525755_18057087_f9ec0c73_2c297f80_7f317190_80f9ec08;
defparam bootram.RAM3.INIT_29=256'h5253fe87_83ffff06_90801370_38f08153_f0812584_538a3972_86388fff_8fff7325;
defparam bootram.RAM3.INIT_2A=256'h80c07370_dc705454_e33f80f9_528151e3_fa3fb8ef_908051fd_04fd3d0d_3f883d0d;
defparam bootram.RAM3.INIT_2B=256'h81b0800c_150c810b_0c800b94_800b9015_2398e5ea_800b8415_90732382_82055523;
defparam bootram.RAM3.INIT_2C=256'h74177033_9d055755_80028405_5199e83f_80c05268_3d705457_ea3d0d88_853d0d04;
defparam bootram.RAM3.INIT_2D=256'h81068538_81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381;
defparam bootram.RAM3.INIT_2E=256'h54845279_863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39;
defparam bootram.RAM3.INIT_2F=256'h74800c89_83388155_2e098106_3f800875_73519ef8_80e6e052_80558453_5199983f;
defparam bootram.RAM3.INIT_30=256'h81ff0670_ed3f8008_dbc13f8e_80e6e451_0d92d63f_0c04fc3d_0b81e094_3d0d0481;
defparam bootram.RAM3.INIT_31=256'h883880e7_51515473_2a708106_b408708d_e33f81b8_3f80518d_5255e5aa_5380e784;
defparam bootram.RAM3.INIT_32=256'h80e7fc51_802e9c38_af3f8008_800a51fe_db893f98_80e7d051_3974b738_9c518187;
defparam bootram.RAM3.INIT_33=256'hce398c80_e8b45180_83f93f80_98800a51_a73f7452_82ac51e0_518da93f_daf53f81;
defparam bootram.RAM3.INIT_34=256'h0a5197db_ff528c80_805380ff_c63f8380_e8dc51da_2ebd3880_3f800880_0a51fed1;
defparam bootram.RAM3.INIT_35=256'hd73f8052_82ac51df_51daa03f_3f80e9ac_e73ffed3_82ac51df_51dab03f_3f80e988;
defparam bootram.RAM3.INIT_36=256'h54a05373_fd3d0d75_f9f40c04_0d047180_8a3f863d_e9e851da_3f883980_805183ab;
defparam bootram.RAM3.INIT_37=256'h5372802e_80f9f408_51d8ae3f_3f725272_b451e3e2_735280ea_3880c053_87e82e84;
defparam bootram.RAM3.INIT_38=256'h80f9f408_51d88a3f_80c05280_51d8923f_0da05280_0d04fe3d_722d853d_85387351;
defparam bootram.RAM3.INIT_39=256'h70810651_8008862a_ac3fff0b_0d9a518d_0d04fc3d_722d843d_85388051_5372802e;
defparam bootram.RAM3.INIT_3A=256'h71828024_802e9b38_e4547182_06535580_80088680_ec38820b_71802e80_53548155;
defparam bootram.RAM3.INIT_3B=256'h08528551_8ce73f80_ff548451_802e8338_e8547184_388a3987_71802e8e_8a388a54;
defparam bootram.RAM3.INIT_3C=256'heaec5553_fa800c80_11337080_0780ebac_70830672_80088a2c_882a8c06_8cdf3f71;
defparam bootram.RAM3.INIT_3D=256'h387480f9_f8082e98_3f7480f9_5252d8a3_eee41108_2b8c0680_8a3f7182_515452d8;
defparam bootram.RAM3.INIT_3E=256'h7380f9fc_81069638_74822e09_b93f9e39_06a338fe_812e0981_2ea63874_f80c7482;
defparam bootram.RAM3.INIT_3F=256'h0dd4ca3f_0d04fd3d_ec3f863d_3f99518b_7351fde8_0cfe9f3f_7380f9fc_082e8e38;
defparam bootram.RAM4.INIT_00=256'hf53f81ae_5298518b_8bcb3f8d_fc0c9951_ff0b80f9_80f9f80c_c13f800b_8008518b;
defparam bootram.RAM4.INIT_01=256'h70535484_07f49f06_80089080_518bae3f_de8a3f84_ae528451_8bec3fbe_80529c51;
defparam bootram.RAM4.INIT_02=256'h518b823f_e0f83f80_80eb8451_08537352_2e8d3880_3f738008_84518b99_518bcf3f;
defparam bootram.RAM4.INIT_03=256'h0a0681d0_0a077ed0_0a0681d0_3d0d7cd0_3d0d04f6_8ba83f85_07528051_80088480;
defparam bootram.RAM4.INIT_04=256'h81ab9977_51dbf93f_71770c8a_51dc813f_710c578a_82c08072_83ffff52_0a075956;
defparam bootram.RAM4.INIT_05=256'h51dbd53f_86770c78_805a8199_e33f80e1_0c7851db_82d4e677_ef3f8a59_0c8a51db;
defparam bootram.RAM4.INIT_06=256'h71730707_812a8806_2a840672_2a077183_82067187_0670852a_067081ff_7583ffff;
defparam bootram.RAM4.INIT_07=256'h70818006_872b6306_80c00677_0676852b_077081ff_06717307_74832ba0_73109006;
defparam bootram.RAM4.INIT_08=256'h07077310_88067173_0672812a_71832a84_71872a07_852a8206_7a882a70_73730707;
defparam bootram.RAM4.INIT_09=256'h80067373_6d067081_0677872b_852b80c0_81ff0676_73070770_2ba00671_90067483;
defparam bootram.RAM4.INIT_0A=256'h58525351_5a555b51_53515752_586b4452_6d0c5151_83ffff06_2b7b0770_07077088;
defparam bootram.RAM4.INIT_0B=256'h7081ff06_0676902a_902a9680_daa23f75_770c7851_3f819981_5653daac_5752575d;
defparam bootram.RAM4.INIT_0C=256'h07077310_88067173_0672812a_71832a84_71872a07_852a8206_81ff0670_70730770;
defparam bootram.RAM4.INIT_0D=256'h7081ff06_78872b07_06707207_852b80c0_81ff0676_73070770_2ba00671_90067483;
defparam bootram.RAM4.INIT_0E=256'h680c5156_80067407_882b83fe_872b0770_06710772_852b80c0_10900671_7a882a70;
defparam bootram.RAM4.INIT_0F=256'h0c7851d9_81998577_81a18056_52d9a13f_57515157_58525a5a_51555351_67405b51;
defparam bootram.RAM4.INIT_10=256'h88067173_0672812a_71832a84_71872a07_852a8206_81ff0670_ffff0670_933f7783;
defparam bootram.RAM4.INIT_11=256'h7f067081_0677872b_852b80c0_81ff0676_73070770_2ba00671_90067483_07077310;
defparam bootram.RAM4.INIT_12=256'h71730707_812a8806_2a840672_2a077183_82067187_2a70852a_07077a88_80067373;
defparam bootram.RAM4.INIT_13=256'h70818006_872b6906_80c00677_0676852b_077081ff_06717307_74832ba0_73109006;
defparam bootram.RAM4.INIT_14=256'h5b515852_57525a55_44525351_5151586b_ff066d0c_077083ff_70882b7b_73730707;
defparam bootram.RAM4.INIT_15=256'h96800678_3f77902a_7851d7dc_9983770c_c1805581_d7ea3f81_575c5653_53515752;
defparam bootram.RAM4.INIT_16=256'h812a8806_2a840672_2a077183_82067187_0670852a_077081ff_ff067073_902a7081;
defparam bootram.RAM4.INIT_17=256'h872b6106_80c00677_0676852b_077081ff_06717307_74832ba0_73109006_71730707;
defparam bootram.RAM4.INIT_18=256'h07077088_66067173_0672872b_852b80c0_10900671_7a882a70_73730707_70818006;
defparam bootram.RAM4.INIT_19=256'h515952d6_5a5b5751_53515852_5b515852_69425a54_6a0c5152_83ffff06_2b750770;
defparam bootram.RAM4.INIT_1A=256'h3f80f077_7851d6b8_3f71770c_7851d6c0_3f80770c_5252d6c8_70780c79_d33f9985;
defparam bootram.RAM4.INIT_1B=256'h7851d694_3f71770c_7851d69c_3f71770c_5252d6a4_70780c79_af3f8880_0c7851d6;
defparam bootram.RAM4.INIT_1C=256'h839a3f86_5280d051_fc055380_8254873d_04fb3d0d_3f8c3d0d_7851d68c_3f71770c;
defparam bootram.RAM4.INIT_1D=256'h93269038_59577782_84120858_80d73d08_80d53d08_ffb23d0d_873d0d04_3d22800c;
defparam bootram.RAM4.INIT_1E=256'h80ec8805_38758429_962681a2_9f165675_81ac39ff_51da873f_5280ebbc_77538294;
defparam bootram.RAM4.INIT_1F=256'h5f80c65c_f73f8008_80085e8c_398cf33f_085e818c_c03f8008_80c15ccd_56750804;
defparam bootram.RAM4.INIT_20=256'hfab0518a_17085280_1708538c_80ea3990_5e80d65c_83ffff06_883f8008_80fa39ff;
defparam bootram.RAM4.INIT_21=256'h5cbe3980_863880c4_5675802e_0881ff06_8ae53f80_80fab051_5c80d539_a03f80c5;
defparam bootram.RAM4.INIT_22=256'h05539017_d03dfe80_5ca63980_873f80d7_17085189_1708528c_94175390_c25cb939;
defparam bootram.RAM4.INIT_23=256'h82945580_8339a05c_51f7f83f_5c805280_8f3980d3_3f80d25c_08518c93_08528c17;
defparam bootram.RAM4.INIT_24=256'h887826ec_34811858_57753377_3d790557_771980d2_833d5a58_0554800b_d03dfdec;
defparam bootram.RAM4.INIT_25=256'hf83d0d7a_5183873f_cdf93fff_80ece451_04803d0d_80d03d0d_51e1aa3f_38838082;
defparam bootram.RAM4.INIT_26=256'h81055833_3d347670_5754738a_38758117_807425b7_ff165654_57575874_7c7f7f5a;
defparam bootram.RAM4.INIT_27=256'h51d3953f_ff06548a_3f800881_0651d1a9_527781ff_8a3dfc05_05348253_028405a1;
defparam bootram.RAM4.INIT_28=256'h8338dc56_80de5674_a3053355_fa3d0d02_8a3d0d04_5473800c_38c13981_73802e85;
defparam bootram.RAM4.INIT_29=256'h5702ab05_f93d0d7c_883d0d04_51ff893f_f75280d0_fc055381_8154883d_75883d34;
defparam bootram.RAM4.INIT_2A=256'h5473802e_ff067056_3f800881_5256d0c9_a7053370_fc055202_8153893d_33893d34;
defparam bootram.RAM4.INIT_2B=256'h38815574_73802e83_06705654_800881ff_51cecb3f_537b5275_25973876_9e388077;
defparam bootram.RAM4.INIT_2C=256'hff065574_3f800881_d051ffa0_81f75280_3dfc0553_0d815488_0d04fa3d_800c893d;
defparam bootram.RAM4.INIT_2D=256'h56755574_06833881_de2e0981_56567480_0b883d33_3f953980_f051ccaf_8a3880ec;
defparam bootram.RAM4.INIT_2E=256'h81c0b00c_0c89b00b_0b81c0ac_c0800ca6_80eb0b81_81c0940c_0d04990b_800c883d;
defparam bootram.RAM4.INIT_2F=256'h70812a70_81c0a408_81c0a00c_0c51820b_0781c098_80067081_72882bbe_04803d0d;
defparam bootram.RAM4.INIT_30=256'h810781c0_be800670_0d72882b_0d04803d_800c823d_81c0a808_5170f138_81065151;
defparam bootram.RAM4.INIT_31=256'hf138823d_51515170_2a708106_a4087081_a00c81c0_840b81c0_81c09c0c_980c5173;
defparam bootram.RAM4.INIT_32=256'h83065271_718a3872_75830652_57719138_06555557_7a7c7283_fa3d0d78_0d04ff39;
defparam bootram.RAM4.INIT_33=256'h08720c52_11771270_73822b77_75279438_72555573_3f72822a_815189b2_802e8638;
defparam bootram.RAM4.INIT_34=256'h5353c9c3_11335451_0680ed90_842a708f_3d0d7470_3d0d04fe_54e93988_54528114;
defparam bootram.RAM4.INIT_35=256'h0870882a_5382e090_0d8386d0_0d04fe3d_b63f843d_335253c9_80ed9011_3f728f06;
defparam bootram.RAM4.INIT_36=256'hfc3d0d02_843d0d04_51ca803f_3880eda0_135372e9_2e8e38ff_51527180_70810651;
defparam bootram.RAM4.INIT_37=256'h2a708106_90087088_d05382e0_55558386_80c08007_8c800607_80ff067c_9b05337a;
defparam bootram.RAM4.INIT_38=256'he0900c77_800c7382_3f7882e0_a051c9c3_e93880ed_ff135372_802e8e38_51515271;
defparam bootram.RAM4.INIT_39=256'h90087088_d05382e0_a9388386_5274802e_e0900c74_82800782_e0980c73_81ff0682;
defparam bootram.RAM4.INIT_3A=256'h08527180_3f82e080_a051c8ff_e93880ed_ff135372_802e8e38_51515271_2a708106;
defparam bootram.RAM4.INIT_3B=256'h863d0d04_51fee13f_53805280_55885480_940c8880_810b82e0_04fc3d0d_0c863d0d;
defparam bootram.RAM4.INIT_3C=256'h04fc3d0d_0c863d0d_81ff0680_cb3f8008_528151fe_8a805381_80559054_fc3d0d88;
defparam bootram.RAM4.INIT_3D=256'h06800c82_08813281_0dca3f80_0d04803d_af3f863d_528051fe_54865381_88805588;
defparam bootram.RAM4.INIT_3E=256'h85923f75_3d0d7756_3d0d04fb_2ef43882_06517080_800881ff_3d0deb3f_3d0d0480;
defparam bootram.RAM4.INIT_3F=256'hfdde3f87_81528051_9b0a0753_fe9b0a06_55a05475_b43f8880_38dd3fff_8008269b;
defparam bootram.RAM5.INIT_00=256'h38751754_ff2681b4_80557381_11565757_cb3d08ff_c93d0880_ba3d0d80_3d0d04ff;
defparam bootram.RAM5.INIT_01=256'h3d085273_755380cb_548cbe3f_883d7052_5381ff52_a7388280_80082681_84ce3f73;
defparam bootram.RAM5.INIT_02=256'h0a0680c0_0c76fec0_0b82e090_980c8880_3f7482e0_d43ffce6_fefd3ffe_518b993f;
defparam bootram.RAM5.INIT_03=256'h3f80c83d_900cfcb6_a00b82e0_e0900c8a_88a00b82_82e0980c_800c810b_0a0782e0;
defparam bootram.RAM5.INIT_04=256'h82e0840c_88157008_880c54fe_700882e0_54fe8415_82e08c0c_80157008_558f56fe;
defparam bootram.RAM5.INIT_05=256'hff169016_0cfbf73f_0b82e090_900c8a80_800b82e0_800c5488_700882e0_54fe8c15;
defparam bootram.RAM5.INIT_06=256'h7b7d7212_f93d0d79_c83d0d04_74800c80_980c8155_800b82e0_25ffbc38_56567580;
defparam bootram.RAM5.INIT_07=256'h5473802e_7581ff06_2e80c338_81577480_2680cb38_57738008_838a3f80_575a5656;
defparam bootram.RAM5.INIT_08=256'h19767631_3f731674_7551fdeb_77537352_83387654_57767527_74317555_a2388280;
defparam bootram.RAM5.INIT_09=256'h0c893d0d_81577680_39fd8c3f_828054dc_7527e138_74548280_802e8e38_57595674;
defparam bootram.RAM5.INIT_0A=256'h0b88160c_27903880_3f800874_1354829c_2e8d3873_54557380_76787a56_04fc3d0d;
defparam bootram.RAM5.INIT_0B=256'h08307276_81ec3f80_16565152_707406ff_3f800830_a63981fa_0c80750c_800b8416;
defparam bootram.RAM5.INIT_0C=256'h0881ff06_fc983f80_3d0d7554_3d0d04fd_fcc93f86_160c7151_160c7188_0c740684;
defparam bootram.RAM5.INIT_0D=256'h7088160c_08800805_b13f8814_2e943881_08841508_81538814_802e9f38_70545271;
defparam bootram.RAM5.INIT_0E=256'h51f9fd3f_53815281_5481f90a_888055a0_04fc3d0d_0c853d0d_80537280_51fc943f;
defparam bootram.RAM5.INIT_0F=256'h882a7081_d43f8008_7480c238_fa840855_fb3d0d80_863d0d04_0a06800c_8008fe80;
defparam bootram.RAM5.INIT_10=256'h7380c02e_83388155_3f73a02e_5154cdbe_edbc5458_56715580_81ff0670_ff068008;
defparam bootram.RAM5.INIT_11=256'h08ea1155_0c80fa84_7580fa84_fe3f9c39_edd451c2_2e8a3880_06547380_93387481;
defparam bootram.RAM5.INIT_12=256'h800880ee_04ff913f_0c873d0d_dc3f7480_cd843ff4_80edf451_8d387452_55827427;
defparam bootram.RAM5.INIT_13=256'h3d0d7d56_800c04f6_0b80082b_fefa3f81_2b800c04_810b8008_0c04f23f_de053380;
defparam bootram.RAM5.INIT_14=256'h0c810b82_2b82e080_840c7c88_8b0b82e0_82e0900c_0c88800b_0b82e098_f8b03f80;
defparam bootram.RAM5.INIT_15=256'hd3388880_73762780_7e558054_0cf7ff3f_0b82e090_900c8aa8_a80b82e0_e0980c88;
defparam bootram.RAM5.INIT_16=256'h085a82e0_5982e084_82e08808_e08c0858_f7e43f82_82e0900c_0c8a800b_0b82e090;
defparam bootram.RAM5.INIT_17=256'h51703375_91387117_52717327_38705380_70732783_52579053_3d767531_80085b88;
defparam bootram.RAM5.INIT_18=256'h0d7251f6_0d04803d_980c8c3d_800b82e0_54ffa939_ec397214_34811252_70810557;
defparam bootram.RAM5.INIT_19=256'h0870800c_82de3f80_88050851_08528c08_8c088c05_3d0d8053_028c0cfd_a13f8c08;
defparam bootram.RAM5.INIT_1A=256'h5182b93f_08880508_0508528c_538c088c_fd3d0d81_08028c0c_8c0c048c_54853d0d;
defparam bootram.RAM5.INIT_1B=256'h08880508_fc050c8c_800b8c08_0cf93d0d_8c08028c_0d8c0c04_0c54853d_80087080;
defparam bootram.RAM5.INIT_1C=256'h38810b8c_fc050888_050c8c08_0b8c08f4_88050c80_08308c08_8c088805_8025ab38;
defparam bootram.RAM5.INIT_1D=256'h308c088c_088c0508_25ab388c_8c050880_050c8c08_088c08fc_8c08f405_08f4050c;
defparam bootram.RAM5.INIT_1E=256'h8c08fc05_08f00508_f0050c8c_810b8c08_05088838_0c8c08fc_8c08f005_050c800b;
defparam bootram.RAM5.INIT_1F=256'h08fc0508_050c548c_708c08f8_a73f8008_05085181_528c0888_088c0508_0c80538c;
defparam bootram.RAM5.INIT_20=256'h0c048c08_893d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805_802e8c38;
defparam bootram.RAM5.INIT_21=256'h8c088805_88050830_93388c08_05088025_0c8c0888_8c08fc05_3d0d800b_028c0cfb;
defparam bootram.RAM5.INIT_22=256'h81538c08_088c050c_0508308c_388c088c_0880258c_8c088c05_08fc050c_0c810b8c;
defparam bootram.RAM5.INIT_23=256'h8c388c08_0508802e_548c08fc_08f8050c_8008708c_0851ad3f_8c088805_8c050852;
defparam bootram.RAM5.INIT_24=256'h0cfd3d0d_8c08028c_0d8c0c04_0c54873d_05087080_0c8c08f8_8c08f805_f8050830;
defparam bootram.RAM5.INIT_25=256'h08fc0508_27ac388c_08880508_8c05088c_050c8c08_0b8c08f8_fc050c80_810b8c08;
defparam bootram.RAM5.INIT_26=256'h0508108c_0c8c08fc_8c088c05_8c050810_99388c08_8c050824_800b8c08_802ea338;
defparam bootram.RAM5.INIT_27=256'h388c0888_050826a1_088c0888_8c088c05_2e80c938_fc050880_c9398c08_08fc050c;
defparam bootram.RAM5.INIT_28=256'h0c8c08fc_8c08f805_fc050807_05088c08_0c8c08f8_8c088805_8c050831_05088c08;
defparam bootram.RAM5.INIT_29=256'h08802e8f_8c089005_0cffaf39_8c088c05_0508812a_0c8c088c_8c08fc05_0508812a;
defparam bootram.RAM5.INIT_2A=256'h08f40508_050c518c_708c08f4_08f80508_518d398c_08f4050c_0508708c_388c0888;
defparam bootram.RAM5.INIT_2B=256'h70802eb0_07830651_8c387474_52837227_77795656_fc3d0d78_0d8c0c04_800c853d;
defparam bootram.RAM5.INIT_2C=256'h14545555_158115ff_06bd3881_712e0981_33525372_38743374_71ff2ea0_38ff1252;
defparam bootram.RAM5.INIT_2D=256'h8f388411_2e098106_70087308_74745451_863d0d04_800b800c_8106e238_71ff2e09;
defparam bootram.RAM5.INIT_2E=256'hfc3d0d76_863d0d04_7131800c_ffaf3972_70735555_8326e938_54545171_8414fc14;
defparam bootram.RAM5.INIT_2F=256'h2e983872_125271ff_2ea738ff_06517080_72750783_72278c38_5555558f_70797b55;
defparam bootram.RAM5.INIT_30=256'h04745172_0c863d0d_ea387480_2e098106_125271ff_055634ff_33747081_70810554;
defparam bootram.RAM5.INIT_31=256'h08717084_70840554_05530c72_08717084_70840554_05530c72_08717084_70840554;
defparam bootram.RAM5.INIT_32=256'h72708405_72279538_26c93883_1252718f_05530cf0_08717084_70840554_05530c72;
defparam bootram.RAM5.INIT_33=256'h8c059f05_76797102_39fc3d0d_7054ff83_8326ed38_fc125271_8405530c_54087170;
defparam bootram.RAM5.INIT_34=256'h73708105_2e933873_125271ff_2ea238ff_06517080_8a387483_55837227_33575553;
defparam bootram.RAM5.INIT_35=256'h902b0751_75077071_7474882b_863d0d04_3874800c_098106ef_5271ff2e_5534ff12;
defparam bootram.RAM5.INIT_36=256'h72717084_8405530c_0c727170_70840553_530c7271_71708405_27a53872_54518f72;
defparam bootram.RAM5.INIT_37=256'h26f23870_12527183_05530cfc_72717084_72279038_26dd3883_1252718f_05530cf0;
defparam bootram.RAM5.INIT_38=256'h802e80d4_83065170_38717407_802e80d9_55555272_7a7c7054_fa3d0d78_53ff9039;
defparam bootram.RAM5.INIT_39=256'h387081ff_802e8187_06a93872_712e0981_33565174_38713374_72ff2eb1_38ff1353;
defparam bootram.RAM5.INIT_3A=256'h33565170_38713374_098106d1_5272ff2e_ff155555_81128115_2e80fc38_06517080;
defparam bootram.RAM5.INIT_3B=256'h38710874_83732788_71745755_883d0d04_5270800c_71315152_81ff0671_81ff0675;
defparam bootram.RAM5.INIT_3C=256'h0670f884_fbfdff12_087009f7_2eb13874_13537280_ff9739fc_74765552_082e8838;
defparam bootram.RAM5.INIT_3D=256'h74765552_082ed038_38740876_837327d0_84175755_9a388415_51515170_82818006;
defparam bootram.RAM5.INIT_3E=256'h80fa880c_2e9e3873_54547281_80eeb408_3d0d800b_3d0d04fd_0b800c88_fedf3980;
defparam bootram.RAM5.INIT_3F=256'h0cffa8e0_7280fa88_51f6a33f_893f8008_8151ffb0_80eef852_ffa8993f_ffa8fd3f;
defparam bootram.RAM6.INIT_00=256'hef800bfc_ff3d0d80_3f00ff39_0851f686_afec3f80_528151ff_3f80eef8_3fffa7fc;
defparam bootram.RAM6.INIT_01=256'h0d0404ff_f138833d_2e098106_525270ff_fc127008_9138702d_5270ff2e_05700852;
defparam bootram.RAM6.INIT_02=256'h636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_a98b3f04;
defparam bootram.RAM6.INIT_03=256'h6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e;
defparam bootram.RAM6.INIT_04=256'h6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d;
defparam bootram.RAM6.INIT_05=256'h70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f;
defparam bootram.RAM6.INIT_06=256'h74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070;
defparam bootram.RAM6.INIT_07=256'h203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000;
defparam bootram.RAM6.INIT_08=256'h720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000;
defparam bootram.RAM6.INIT_09=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741;
defparam bootram.RAM6.INIT_0A=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d;
defparam bootram.RAM6.INIT_0B=256'h7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000;
defparam bootram.RAM6.INIT_0C=256'h0000078f_00000765_0000078f_0000078f_000006df_000006f6_00000000_65743a20;
defparam bootram.RAM6.INIT_0D=256'h0000066d_0000078f_000006a7_00000713_0000078f_0000078f_0000078f_0000078f;
defparam bootram.RAM6.INIT_0E=256'h00000738_00000733_0000072e_0000067a_0000078f_0000078f_0000078f_0000078f;
defparam bootram.RAM6.INIT_0F=256'h6e203d20_7273696f_70207665_20636869_4c4d5331_00000753_00000746_0000073f;
defparam bootram.RAM6.INIT_10=256'h30782578_6e203d20_7273696f_70207665_20636869_4c4d5332_0a000000_30782578;
defparam bootram.RAM6.INIT_11=256'h6932635f_01c300e2_054a0387_15290a94_3fff0000_0050c285_c0a80a02_0a000000;
defparam bootram.RAM6.INIT_12=256'h5f666f72_77616974_21000000_696c6564_47206661_4348444f_20574154_72656164;
defparam bootram.RAM6.INIT_13=256'h77726974_6932635f_64210000_61696c65_4f472066_54434844_72205741_5f786665;
defparam bootram.RAM6.INIT_14=256'h642e2564_25642e25_45000000_64210000_61696c65_4f472066_54434844_65205741;
defparam bootram.RAM6.INIT_15=256'hffff0000_ffffffff_00000000_43444546_38394142_34353637_30313233_2e256400;
defparam bootram.RAM6.INIT_16=256'h656e2061_6f66206c_656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64;
defparam bootram.RAM6.INIT_17=256'h65642074_6661696c_6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f;
defparam bootram.RAM6.INIT_18=256'h0a68616e_00000000_666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869;
defparam bootram.RAM6.INIT_19=256'h55445020_0a000000_3d202564_697a6520_72642073_20776569_6172703a_646c655f;
defparam bootram.RAM6.INIT_1A=256'h00000000_2025640a_3a202564_67746873_206c656e_74656e74_6e736973_696e636f;
defparam bootram.RAM6.INIT_1B=256'h616c697a_6e697469_656e2069_73206265_68206861_466c6173_53504920_0b0b0b0b;
defparam bootram.RAM6.INIT_1C=256'h53746172_640a0000_203d2025_6d616765_6f6e2069_75637469_50726f64_65640000;
defparam bootram.RAM6.INIT_1D=256'h64696e67_204c6f61_6f64652e_6665206d_6e207361_52582069_20556d54_74696e67;
defparam bootram.RAM6.INIT_1E=256'h2076616c_20666f72_6b696e67_43686563_72652e00_726d7761_65206669_20736166;
defparam bootram.RAM6.INIT_1F=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070;
defparam bootram.RAM6.INIT_20=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072;
defparam bootram.RAM6.INIT_21=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d;
defparam bootram.RAM6.INIT_22=256'h56616c69_2e0a0000_6f756e64_67652066_20696d61_46504741_696f6e20_64756374;
defparam bootram.RAM6.INIT_23=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072;
defparam bootram.RAM6.INIT_24=256'h61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67;
defparam bootram.RAM6.INIT_25=256'h6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765_6e672069;
defparam bootram.RAM6.INIT_26=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20;
defparam bootram.RAM6.INIT_27=256'h6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065;
defparam bootram.RAM6.INIT_28=256'h746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20_20666f75_77617265;
defparam bootram.RAM6.INIT_29=256'h7420746f_64207365_53706565_2e000000_77617265_6669726d_2d696e20_75696c74;
defparam bootram.RAM6.INIT_2A=256'h58000000_57455f52_58000000_57455f54_00000000_4e4f4e45_00000000_2025640a;
defparam bootram.RAM6.INIT_2B=256'h6e74726f_7720636f_20666c6f_726e6574_65746865_43000000_45545249_53594d4d;
defparam bootram.RAM6.INIT_2C=256'h7825782c_74652030_2077726f_4144563a_4e45475f_4155544f_5048595f_6c3a2000;
defparam bootram.RAM6.INIT_2D=256'h21457272_00030203_00000001_00030003_00000000_780a0000_20307825_20676f74;
defparam bootram.RAM6.INIT_2E=256'h20457870_6c65723a_68616e64_6b657420_20706163_64617465_6e207570_6f722069;
defparam bootram.RAM6.INIT_2F=256'h20676f74_20627574_2025642c_6e677468_64206c65_796c6f61_64207061_65637465;
defparam bootram.RAM6.INIT_30=256'h000023f1_00002413_00002428_0000247a_0000247a_000023e4_00000000_2025640a;
defparam bootram.RAM6.INIT_31=256'h0000247a_0000247a_0000247a_0000247a_0000247a_0000247a_0000247a_0000247a;
defparam bootram.RAM6.INIT_32=256'h00002403_0000247a_0000247a_0000246e_00002457_0000247a_0000247a_0000247a;
defparam bootram.RAM6.INIT_33=256'h61642073_6f207265_65642074_4661696c_00000000_6f72740a_0a0a6162_00002444;
defparam bootram.RAM6.INIT_34=256'h43444546_38394142_34353637_30313233_67000000_20666c61_626f6f74_61666520;
defparam bootram.RAM6.INIT_35=256'h0a666c61_64210000_61696c65_4f472066_54434844_74205741_5f776169_73706966;
defparam bootram.RAM6.INIT_36=256'h6c617368_6e672066_0a57726f_25640a00_697a653d_25642073_7970653d_73682074;
defparam bootram.RAM6.INIT_37=256'h6c617368_6e672066_0a57726f_00000000_6e67210a_63687475_652e2041_20747970;
defparam bootram.RAM6.INIT_38=256'h65000000_792e6578_64756d6d_67210a00_6874756e_64204163_653a2025_2073697a;
defparam bootram.RAM6.INIT_39=256'h00003788_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff;
defparam bootram.RAM6.INIT_3A=256'h000c0000_00190010_ffff0033_04000400_01010100_3fff0000_0050c285_c0a80a02;
defparam bootram.RAM6.INIT_3B=256'hffffffff_00003714_10101200_00003560_00003558_00003550_00003548_03197500;
defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_ffffffff_00000000;
defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;

52
fpga/top/UmTRX/coregen/fifo_axi_36.gise
View File

@@ -1,52 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_axi_36.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_axi_36.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_axi_36.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1501582277" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1501582277">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8970095556748691462" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1830686490926110834" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1501588912" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5214082714422500266" xil_pn:start_ts="1501588912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>

491
fpga/top/UmTRX/coregen/fifo_axi_36.v
View File

@@ -1,491 +0,0 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file fifo_axi_36.v when simulating
// the core, fifo_axi_36. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module fifo_axi_36(
m_aclk,
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tuser
);
input m_aclk;
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [31 : 0] s_axis_tdata;
input [3 : 0] s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [31 : 0] m_axis_tdata;
output [3 : 0] m_axis_tuser;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(36),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(1),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(32765),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(32767),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(32768),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(15),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.M_ACLK(m_aclk),
.S_ACLK(s_aclk),
.S_ARESETN(s_aresetn),
.S_AXIS_TVALID(s_axis_tvalid),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.S_AXIS_TUSER(s_axis_tuser),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TREADY(m_axis_tready),
.M_AXIS_TDATA(m_axis_tdata),
.M_AXIS_TUSER(m_axis_tuser),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.DIN(),
.WR_EN(),
.RD_EN(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.DOUT(),
.FULL(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.EMPTY(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule

213
fpga/top/UmTRX/coregen/fifo_axi_36.xco
View File

@@ -1,213 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Tue Aug 1 09:18:38 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx75
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Independent_Clock
CSET component_name=fifo_axi_36
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=32765
CSET empty_threshold_assert_value_rach=13
CSET empty_threshold_assert_value_rdch=1021
CSET empty_threshold_assert_value_wach=13
CSET empty_threshold_assert_value_wdch=1021
CSET empty_threshold_assert_value_wrch=13
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=true
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=true
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Independent_Clocks_Block_RAM
CSET fifo_implementation_rach=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_rdch=Independent_Clocks_Block_RAM
CSET fifo_implementation_wach=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_wdch=Independent_Clocks_Block_RAM
CSET fifo_implementation_wrch=Independent_Clocks_Distributed_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1022
CSET full_threshold_assert_value_axis=32767
CSET full_threshold_assert_value_rach=15
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=15
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=15
CSET full_threshold_negate_value=1021
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=18
CSET input_depth=1024
CSET input_depth_axis=32768
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=AXI4
CSET output_data_width=18
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=32
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: ef6b9ccd

73
fpga/top/UmTRX/coregen/fifo_axi_36.xise
View File

@@ -1,73 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_axi_36.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="fifo_axi_36.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="fifo_axi_36.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_axi_36" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-08-01T12:21:22" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A42A837D86A509961F66E126F05239A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

28
fpga/top/UmTRX/mapextraeffortioreg.xds
View File

@@ -1,28 +0,0 @@
<DesignStrategy goal="Timing Performance" strategy="SmartXplorer - mapextraeffortioreg" version="14.7">
<Description><![CDATA[ This is a Timing Performance optimized strategy.This strategy is also one of the strategies used by SmartXplorer. If you wish to run SmartXplorer to automatically try multiple Timing Performance strategies, including this one, close this dialog and then select Tools -> SmartXplorer -> Launch SmartXplorer . ]]></Description>
<DeviceList devices="spartan6,spartan6l,aspartan6,qspartan6,qspartan6l" />
<Properties>
<property name = "Map:Placer Effort Level"
value = "High" />
<property name = "Map:Placer Extra Effort"
value = "Normal" />
<property name = "Map:Pack I/O Registers/Latches into IOBs"
value = "For Inputs and Outputs" />
<property name = "Map:Starting Placer Cost Table (1-100)"
value = "24" />
<property name = "Place &amp; Route:Place &amp; Route Effort Level (Overall)"
value = "High" />
<property name = "Place &amp; Route:Extra Effort (Highest PAR level only)"
value = "Normal" />
<property name = "Generate Post-Place &amp; Route Static Timing:Number of Paths in Error/Verbose Report"
value = "10" />
<property name = "Generate Post-Place &amp; Route Static Timing:Report Type"
value = "Error Report" />
<property name = "Generate Post-Place &amp; Route Static Timing:Change Device Speed To"
value = "-2" />
<property name = "Generate Post-Place &amp; Route Static Timing:Report Paths by Endpoint"
value = "3" />
<property name = "Generate Post-Place &amp; Route Static Timing:Report Fastest Path(s) in Each Constraint"
value = "true" />
</Properties>
</DesignStrategy>

23
fpga/top/UmTRX/u2plus_umtrx_v2.v
View File

@@ -216,18 +216,15 @@ wire DivSw1, DivSw2;
// Status and control signals
.LOCKED_OUT(led_stat)); // OUT
wire clk_rx_div2;
pll_rx pll_rx_instance
(// Clock in ports
.gmii_rx_clk(GMII_RX_CLK), // IN
// Clock out ports
.clk_rx(clk_rx), // OUT
.clk_to_mac(CLK_TO_MAC_int2), // OUT
.clk_rx_180(clk_rx_180),
.clk_rx_div2(clk_rx_div2)); // OUT
.clk_rx_180(clk_rx_180)); // OUT
`ifndef NO_EXT_FIFO
OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
.C0(clk270_100_buf),
.C1(~clk270_100_buf),
@@ -236,17 +233,7 @@ wire DivSw1, DivSw2;
.D1(1'b0),
.R(1'b0),
.S(1'b0));
`else
assign RAM_A = 0;
assign RAM_BWn = ~0;
assign RAM_ZZ = 1;
assign RAM_LDn = 1;
assign RAM_OEn = 1;
assign RAM_WEn = 1;
assign RAM_CENn = 1;
assign RAM_CLK = 1;
`endif
// I2C -- Don't use external transistors for open drain, the FPGA implements this
IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
@@ -289,7 +276,7 @@ wire DivSw1, DivSw2;
.R(0), // Synchronous reset input
.S(0) // Synchronous preset input
);
//
// Instantiate IO for Bidirectional bus to SRAM
@@ -348,7 +335,7 @@ wire DivSw1, DivSw2;
end
umtrx_core u2p_c(
.sys_clk (clk_rx_div2),
.sys_clk (dsp_clk),
.dsp_clk (lms_clk),
.fe_clk (clk_icap), //1/2 dsp rate
.wb_clk (wb_clk),

187
fpga/top/UmTRX/umtrx_core.v
View File

@@ -174,10 +174,6 @@ module umtrx_core
wire [7:0] set_addr, set_addr_dsp, set_addr_sys, set_addr_fe, set_addr_udp_wb, set_addr_udp_sys;
wire [31:0] set_data, set_data_dsp, set_data_sys, set_data_fe, set_data_udp_wb, set_data_udp_sys;
wire set_stb, set_stb_dsp, set_stb_sys, set_stb_fe, set_stb_udp_wb, set_stb_udp_sys;
wire set_stb_dsp0, set_stb_dsp1;
wire [31:0] set_data_dsp0, set_data_dsp1;
wire [7:0] set_addr_dsp0, set_addr_dsp1;
reg wb_rst;
wire dsp_rst, sys_rst, fe_rst;
@@ -416,80 +412,17 @@ module umtrx_core
// /////////////////////////////////////////////////////////////////////////
// SPI -- Slave #2
reg [31:0] spi_readback0;
reg [31:0] spi_readback1;
wire [31:0] spi_debug;
wire [31:0] spi_readback;
wire spi_ready;
wire [0:0] AXIS_SPI_CONFIG_tdest;
wire [79:0] AXIS_SPI_CONFIG_tdata;
wire AXIS_SPI_CONFIG_tvalid;
wire AXIS_SPI_CONFIG_tready;
wire [0:0] AXIS_SPI_READBACK_tdest;
wire [31:0] AXIS_SPI_READBACK_tdata;
wire AXIS_SPI_READBACK_tvalid;
wire AXIS_SPI_READBACK_tready;
axis_spi_core #(.DESTW(1), .WIDTH(5), .DEBUG(0)) axis_shared_spi(
simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(5)) shared_spi(
.clock(dsp_clk), .reset(dsp_rst),
.CONFIG_tdest(AXIS_SPI_CONFIG_tdest),
.CONFIG_tdata(AXIS_SPI_CONFIG_tdata),
.CONFIG_tvalid(AXIS_SPI_CONFIG_tvalid),
.CONFIG_tready(AXIS_SPI_CONFIG_tready),
.READBACK_tdest(AXIS_SPI_READBACK_tdest),
.READBACK_tdata(AXIS_SPI_READBACK_tdata),
.READBACK_tvalid(AXIS_SPI_READBACK_tvalid),
.READBACK_tready(AXIS_SPI_READBACK_tready),
.set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
.readback(spi_readback), .ready(spi_ready),
.sen({aux_sen2,aux_sen1,sen_dac,sen_lms2,sen_lms1}),
.sclk(sclk), .mosi(mosi), .miso(miso)
.sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug)
);
//setting register block for spi dest 0 (wishbone) and spi dest 1 (ctrl fifo)
//Note: the strobes are exclusive (settings fifo cross clock)
wire [79:0] spi_config [0:1];
wire [0:1] spi_trigger;
wire [0:1] set_stb_dsp_n = {set_stb_dsp0, set_stb_dsp1};
genvar i;
generate for (i=0; i <= 1; i=i+1) begin
setting_reg #(.my_addr(SR_SPI_CORE+2),.width(32)) axis_shared_spi_sr0(
.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
.out(spi_config[i][31:0]),.changed(spi_trigger[i]));
setting_reg #(.my_addr(SR_SPI_CORE+1),.width(32)) axis_shared_spi_sr1(
.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
.out(spi_config[i][63:32]),.changed());
setting_reg #(.my_addr(SR_SPI_CORE+0),.width(16)) axis_shared_spi_sr2(
.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp_n[i]),.addr(set_addr_dsp),.in(set_data_dsp),
.out(spi_config[i][79:64]),.changed());
end endgenerate
//assign config bus from setting register sources
//Note: the triggers are exclusive (settings fifo cross clock)
assign AXIS_SPI_CONFIG_tdest = (spi_trigger[0])?1'b0:1'b1;
assign AXIS_SPI_CONFIG_tdata = (spi_trigger[0])?spi_config[0]:spi_config[1];
assign AXIS_SPI_CONFIG_tvalid = (spi_trigger != 0);
//create spi ready to block the ctrl fifo ASAP
wire spi_ready_now = AXIS_SPI_CONFIG_tready && !AXIS_SPI_CONFIG_tvalid;
assign spi_ready = spi_ready_now && spi_ready_prev;
reg spi_ready_prev;
always @(posedge dsp_clk) begin
spi_ready_prev <= spi_ready_now;
end
//readback output bus latches values into readback register
assign AXIS_SPI_READBACK_tready = 1'b1;
always @(posedge dsp_clk) begin
if (AXIS_SPI_READBACK_tvalid && AXIS_SPI_READBACK_tready) begin
if (AXIS_SPI_READBACK_tdest == 1'b0) spi_readback0 <= AXIS_SPI_READBACK_tdata;
if (AXIS_SPI_READBACK_tdest == 1'b1) spi_readback1 <= AXIS_SPI_READBACK_tdata;
end
end
// /////////////////////////////////////////////////////////////////////////
// I2C -- Slave #3
i2c_master_top #(.ARST_LVL(1))
@@ -515,7 +448,7 @@ module umtrx_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
localparam compat_num = {16'd9, 16'd3}; //major, minor
localparam compat_num = {16'd9, 16'd2}; //major, minor
wire [31:0] irq_readback = {16'b0, aux_ld2, aux_ld1, button, spi_ready, 12'b0};
@@ -523,7 +456,7 @@ module umtrx_core
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
.word00(spi_readback0),.word01(`NUMDDC),.word02(`NUMDUC),.word03(32'b0),
.word00(spi_readback),.word01(`NUMDDC),.word02(`NUMDUC),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09(32'b0),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback),
@@ -565,6 +498,10 @@ module umtrx_core
(.clk_i(dsp_clk), .rst_i(dsp_rst), .set_stb_i(set_stb_dsp), .set_addr_i(set_addr_dsp), .set_data_i(set_data_dsp),
.clk_o(fe_clk), .rst_o(fe_rst), .set_stb_o(set_stb_fe), .set_addr_o(set_addr_fe), .set_data_o(set_data_fe));
wire set_stb_dsp0, set_stb_dsp1;
wire [31:0] set_data_dsp0, set_data_dsp1;
wire [7:0] set_addr_dsp0, set_addr_dsp1;
//mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
@@ -605,7 +542,7 @@ module umtrx_core
.in_data(ctrl_data_dsp), .in_valid(ctrl_valid_dsp), .in_ready(ctrl_ready_dsp),
.out_data(resp_data_dsp), .out_valid(resp_valid_dsp), .out_ready(resp_ready_dsp),
.strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1),
.word00(spi_readback1),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word00(spi_readback),.word01(32'b0),.word02(32'b0),.word03(32'b0),
.word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(32'b0),.word09(32'b0),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(32'b0),.word13(irq_readback),
@@ -624,13 +561,8 @@ module umtrx_core
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear));
wire sram_clear;
`ifdef INTERNAL_FIFOS
setting_reg #(.my_addr(SR_MISC+2),.width(1)) sr_sram_clear
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sram_clear));
`else
setting_reg #(.my_addr(SR_MISC+2),.width(1)) sr_sram_clear
(.clk(sys_clk),.rst(sys_rst),.strobe(set_stb_sys),.addr(set_addr_sys),.in(set_data_sys),.changed(sram_clear));
`endif
setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(phy_reset),.changed());
@@ -901,15 +833,10 @@ module umtrx_core
);
// /////////////////////////////////////////////////////////////////////////
// TX chains
wire [35:0] vita0_data_dsp;
wire vita0_valid_dsp;
wire vita0_ready_dsp;
wire [35:0] vita1_data_dsp;
wire vita1_valid_dsp;
wire vita1_ready_dsp;
// TX chains
wire [35:0] sram0_data, sram1_data;
wire sram0_valid, sram1_valid;
wire sram0_ready, sram1_ready;
wire run_tx_dsp0, run_tx_dsp1;
//switch to select frontend used per DSP
@@ -941,12 +868,12 @@ module umtrx_core
.set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp),
.set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe),
.front_i(dac0_a_int), .front_q(dac0_b_int), .dac_stb(dac0_strobe), .run(run_tx_dsp0),
.vita_data_dsp(vita0_data_dsp), .vita_valid_dsp(vita0_valid_dsp), .vita_ready_dsp(vita0_ready_dsp),
.vita_data_sys(sram0_data), .vita_valid_sys(sram0_valid), .vita_ready_sys(sram0_ready),
.err_data_sys(err_tx0_data), .err_valid_sys(err_tx0_valid), .err_ready_sys(err_tx0_ready),
.vita_time(vita_time)
);
end else begin
assign vita0_ready_dsp = 1;
assign sram0_ready = 1;
assign err_tx0_valid = 0;
assign run_tx_dsp0 = 0;
end
@@ -967,12 +894,12 @@ module umtrx_core
.set_stb_dsp(set_stb_dsp), .set_addr_dsp(set_addr_dsp), .set_data_dsp(set_data_dsp),
.set_stb_fe(set_stb_fe), .set_addr_fe(set_addr_fe), .set_data_fe(set_data_fe),
.front_i(dac1_a_int), .front_q(dac1_b_int), .dac_stb(dac1_strobe), .run(run_tx_dsp1),
.vita_data_dsp(vita1_data_dsp), .vita_valid_dsp(vita1_valid_dsp), .vita_ready_dsp(vita1_ready_dsp),
.vita_data_sys(sram1_data), .vita_valid_sys(sram1_valid), .vita_ready_sys(sram1_ready),
.err_data_sys(err_tx1_data), .err_valid_sys(err_tx1_valid), .err_ready_sys(err_tx1_ready),
.vita_time(vita_time)
);
end else begin
assign vita1_ready_dsp = 1;
assign sram1_ready = 1;
assign err_tx1_valid = 0;
assign run_tx_dsp1 = 0;
end
@@ -996,77 +923,6 @@ module umtrx_core
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
//`define INTERNAL_FIFOS
`ifdef INTERNAL_FIFOS
wire [35:0] vita0_data_cc;
wire [35:0] vita1_data_cc;
wire vita0_valid_cc, vita1_valid_cc;
wire vita0_ready_cc, vita1_ready_cc;
axi_fifo_2clk #(.WIDTH(36), .SIZE(9)) fifo_tx0_sys_dsp
(
.i_aclk(sys_clk), .i_tdata(dsp_tx0_data), .i_tvalid(dsp_tx0_valid), .i_tready(dsp_tx0_ready),
.o_aclk(dsp_clk), .o_tdata(vita0_data_cc), .o_tvalid(vita0_valid_cc), .o_tready(vita0_ready_cc),
.reset(dsp_rst | sys_rst | sram_clear)
);
axi_fifo_2clk #(.WIDTH(36), .SIZE(9)) fifo_tx1_sys_dsp
(
.i_aclk(sys_clk), .i_tdata(dsp_tx1_data), .i_tvalid(dsp_tx1_valid), .i_tready(dsp_tx1_ready),
.o_aclk(dsp_clk), .o_tdata(vita1_data_cc), .o_tvalid(vita1_valid_cc), .o_tready(vita1_ready_cc),
.reset(dsp_rst | sys_rst | sram_clear)
);
fifo_axi_36 ififo0(
.s_aclk(dsp_clk),
.s_aresetn(~((dsp_rst | sram_clear))),
.s_axis_tvalid(vita0_valid_cc),
.s_axis_tready(vita0_ready_cc),
.s_axis_tdata(vita0_data_cc[31:0]),
.s_axis_tuser(vita0_data_cc[35:32]),
.m_aclk(dsp_clk),
.m_axis_tvalid(vita0_valid_dsp),
.m_axis_tready(vita0_ready_dsp),
.m_axis_tdata(vita0_data_dsp[31:0]),
.m_axis_tuser(vita0_data_dsp[35:32])
);
fifo_axi_36 ififo1(
.s_aclk(dsp_clk),
.s_aresetn(~((dsp_rst | sram_clear))),
.s_axis_tvalid(vita1_valid_cc),
.s_axis_tready(vita1_ready_cc),
.s_axis_tdata(vita1_data_cc[31:0]),
.s_axis_tuser(vita1_data_cc[35:32]),
.m_aclk(dsp_clk),
.m_axis_tvalid(vita1_valid_dsp),
.m_axis_tready(vita1_ready_dsp),
.m_axis_tdata(vita1_data_dsp[31:0]),
.m_axis_tuser(vita1_data_dsp[35:32])
);
`else
wire [35:0] sram0_data, sram1_data;
wire sram0_valid, sram1_valid;
wire sram0_ready, sram1_ready;
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_tx0_2clock_vita
(
.i_aclk(sys_clk), .i_tdata(sram0_data), .i_tvalid(sram0_valid), .i_tready(sram0_ready),
.o_aclk(dsp_clk), .o_tdata(vita0_data_dsp), .o_tvalid(vita0_valid_dsp), .o_tready(vita0_ready_dsp),
.reset(dsp_rst | sys_rst)
);
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_tx1_2clock_vita
(
.i_aclk(sys_clk), .i_tdata(sram1_data), .i_tvalid(sram1_valid), .i_tready(sram1_ready),
.o_aclk(dsp_clk), .o_tdata(vita1_data_dsp), .o_tvalid(vita1_valid_dsp), .o_tready(vita1_ready_dsp),
.reset(dsp_rst | sys_rst)
);
`ifndef NO_EXT_FIFO
assign RAM_A[20:19] = 2'b0;
@@ -1111,7 +967,6 @@ module umtrx_core
.dataout_1(sram1_data),
.debug(debug_extfifo),
.debug2(debug_extfifo2) );
`endif
// /////////////////////////////////////////////////////////////////////////
// VITA Timing

22
fpga/top/UmTRX/umtrx_tx_chain.v
View File

@@ -37,10 +37,10 @@ module umtrx_tx_chain
input dac_stb,
output run,
//dsp clock domain
input [35:0] vita_data_dsp,
input vita_valid_dsp,
output vita_ready_dsp,
//sys clock domain
input [35:0] vita_data_sys,
input vita_valid_sys,
output vita_ready_sys,
//sys clock domain
output [35:0] err_data_sys,
@@ -91,15 +91,9 @@ module umtrx_tx_chain
/*******************************************************************
* TX VITA deframer
******************************************************************/
/*
wire [35:0] vita_data_dsp;
wire vita_valid_dsp;
wire vita_ready_dsp;
*/
wire [35:0] err_data_dsp;
wire err_valid_dsp;
wire err_ready_dsp;
wire [35:0] vita_data_dsp, err_data_dsp;
wire vita_valid_dsp, err_valid_dsp;
wire vita_ready_dsp, err_ready_dsp;
vita_tx_chain #(.BASE(CTRL_BASE), .UNIT(PROT_DEST), .FIFOSIZE(FIFOSIZE),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
@@ -120,14 +114,12 @@ module umtrx_tx_chain
/*******************************************************************
* Cross clock fifo from sys to dsp clock domain
******************************************************************/
/*
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_vita
(
.i_aclk(sys_clk), .i_tdata(vita_data_sys), .i_tvalid(vita_valid_sys), .i_tready(vita_ready_sys),
.o_aclk(dsp_clk), .o_tdata(vita_data_dsp), .o_tvalid(vita_valid_dsp), .o_tready(vita_ready_dsp),
.reset(dsp_rst | sys_rst)
);
*/
axi_fifo_2clk #(.WIDTH(36), .SIZE(0)) fifo_2clock_err
(
.i_aclk(dsp_clk), .i_tdata(err_data_dsp), .i_tvalid(err_valid_dsp), .i_tready(err_ready_dsp),

22
host/CMakeLists.txt
View File

@@ -58,7 +58,6 @@ list(APPEND UMTRX_SOURCES
cores/time64_core_200.cpp
cores/validate_subdev_spec.cpp
cores/apply_corrections.cpp
umsel2_ctrl.cpp
)
########################################################################
@@ -112,7 +111,7 @@ SET(Boost_ADDITIONAL_VERSIONS
"1.60.0" "1.60" "1.61.0" "1.61" "1.62.0" "1.62" "1.63.0" "1.63" "1.64.0" "1.64"
"1.65.0" "1.65" "1.66.0" "1.66" "1.67.0" "1.67" "1.68.0" "1.68" "1.69.0" "1.69"
)
FIND_PACKAGE(Boost 1.36 REQUIRED COMPONENTS ${BOOST_REQUIRED_COMPONENTS})
FIND_PACKAGE(Boost 1.36 COMPONENTS ${BOOST_REQUIRED_COMPONENTS})
INCLUDE_DIRECTORIES(${Boost_INCLUDE_DIRS})
LINK_DIRECTORIES(${Boost_LIBRARY_DIRS})
@@ -129,10 +128,6 @@ if (UNIX)
list(APPEND UMTRX_LIBRARIES ${CMAKE_THREAD_LIBS_INIT})
endif()
#make boost property tree thread safe
#http://stackoverflow.com/questions/8156948/is-boostproperty-treeptree-thread-safe
add_definitions(-DBOOST_SPIRIT_THREADSAFE)
########################################################################
# Helpful compiler flags
########################################################################
@@ -151,7 +146,7 @@ if(CMAKE_COMPILER_IS_GNUCXX)
endif()
########################################################################
# UHD compatibility checks
# Look for device filter
########################################################################
message(STATUS "Checking uhd::device::register_device() API...")
message(STATUS " Reading ${UHD_INCLUDE_DIRS}/uhd/device.hpp...")
@@ -164,19 +159,6 @@ else()
message(STATUS " has filter API")
endif()
message(STATUS "Checking uhd::property::set_publisher() API...")
message(STATUS " Reading ${UHD_INCLUDE_DIRS}/uhd/property_tree.hpp...")
file(READ ${UHD_INCLUDE_DIRS}/uhd/property_tree.hpp property_tree_hpp)
string(FIND "${property_tree_hpp}" "set_publisher" has_set_publisher)
if ("${has_set_publisher}" STREQUAL "-1")
message(STATUS " missing set_publisher() API")
else()
add_definitions(-Dpublish=set_publisher)
add_definitions(-Dsubscribe=add_desired_subscriber)
add_definitions(-Dcoerce=add_coerced_subscriber)
message(STATUS " has set_publisher() API")
endif()
########################################################################
# Build the UmTRX module
########################################################################

135
host/lms6002d.cpp
View File

@@ -202,141 +202,6 @@ void lms6002d_dev::set_txrx_polarity_and_interleaving(int rx_fsync_polarity,
lms_write_bits(0x5A, 0xD8, data);
}
void lms6002d_dev::set_dc_calibration_value(uint8_t dc_addr, uint8_t calibration_reg_base, uint8_t value)
{
uint8_t reg_val;
if (verbosity > 0) printf("Manually setting DC Offset Calibration for base %x, ADDR %d: %d\n", calibration_reg_base, dc_addr, value);
// DC_CNTVAL[5:0] = value
write_reg(calibration_reg_base+0x02, value&0x3f);
// Save old register value
reg_val = read_reg(calibration_reg_base+0x03);
// DC_ADDR := ADDR
reg_val = (reg_val & 0xf8) | dc_addr;
write_reg(calibration_reg_base+0x03, reg_val);
// DC_LOAD := 1
reg_val = reg_val | (1 << 4);
write_reg(calibration_reg_base+0x03, reg_val);
// DC_LOAD := 0
reg_val = reg_val ^ (1 << 4);
write_reg(calibration_reg_base+0x03, reg_val);
}
uint8_t lms6002d_dev::get_dc_calibration_value(uint8_t dc_addr, uint8_t calibration_reg_base)
{
// DC_ADDR := ADDR
lms_write_bits(calibration_reg_base+0x03, 0xf8, dc_addr);
uint8_t res = read_reg(calibration_reg_base);
if (verbosity > 0) printf("Reading DC Offset Calibration for base %x, ADDR %d: %d\n", calibration_reg_base, dc_addr, res);
return res;
}
void lms6002d_dev::set_rxfe_dc_i(int8_t value)
{
uint8_t coded_value = (value<0)?(64-value):value;
if (verbosity > 0) printf("Setting DC Offset Calibration for RxFE Channel I to %d (0x%X)\n", value, coded_value);
// DCOFF_I_RXFE := value
lms_write_bits(0x71, 0x7f, coded_value);
}
int8_t lms6002d_dev::get_rxfe_dc_i()
{
uint8_t res = lms_read_shift(0x71, 0x3f, 0);
uint8_t sign = lms_read_shift(0x71, 0x40, 6);
if (verbosity > 0) printf("Reading DC Offset Calibration for RxFE Channel I: sign=%d val=%d)\n", sign, res);
return sign?-res:res;
}
void lms6002d_dev::set_rxfe_dc_q(int8_t value)
{
uint8_t coded_value = (value<0)?(64-value):value;
if (verbosity > 0) printf("Setting DC Offset Calibration for RxFE Channel Q to %d (0x%X)\n", value, coded_value);
// DCOFF_I_RXFE := value
lms_write_bits(0x72, 0x7f, coded_value);
}
int8_t lms6002d_dev::get_rxfe_dc_q()
{
uint8_t res = lms_read_shift(0x72, 0x3f, 0);
uint8_t sign = lms_read_shift(0x72, 0x40, 6);
if (verbosity > 0) printf("Reading DC Offset Calibration for RxFE Channel Q: sign=%d val=%d)\n", sign, res);
return sign?-res:res;
}
void lms6002d_dev::set_rxlpf_dc_i(uint8_t value)
{
set_dc_calibration_value(0, 0x50, value);
}
uint8_t lms6002d_dev::get_rxlpf_dc_i()
{
return get_dc_calibration_value(0, 0x50);
}
void lms6002d_dev::set_rxlpf_dc_q(uint8_t value)
{
set_dc_calibration_value(1, 0x50, value);
}
uint8_t lms6002d_dev::get_rxlpf_dc_q()
{
return get_dc_calibration_value(1, 0x50);
}
void lms6002d_dev::set_rxvga2_dc_reference(uint8_t value)
{
set_dc_calibration_value(0, 0x60, value);
}
uint8_t lms6002d_dev::get_rxvga2_dc_reference()
{
return get_dc_calibration_value(0, 0x60);
}
void lms6002d_dev::set_rxvga2a_dc_i(uint8_t value)
{
set_dc_calibration_value(1, 0x60, value);
}
uint8_t lms6002d_dev::get_rxvga2a_dc_i()
{
return get_dc_calibration_value(1, 0x60);
}
void lms6002d_dev::set_rxvga2a_dc_q(uint8_t value)
{
set_dc_calibration_value(2, 0x60, value);
}
uint8_t lms6002d_dev::get_rxvga2a_dc_q()
{
return get_dc_calibration_value(2, 0x60);
}
void lms6002d_dev::set_rxvga2b_dc_i(uint8_t value)
{
set_dc_calibration_value(3, 0x60, value);
}
uint8_t lms6002d_dev::get_rxvga2b_dc_i()
{
return get_dc_calibration_value(3, 0x60);
}
void lms6002d_dev::set_rxvga2b_dc_q(uint8_t value)
{
set_dc_calibration_value(4, 0x60, value);
}
uint8_t lms6002d_dev::get_rxvga2b_dc_q()
{
return get_dc_calibration_value(4, 0x60);
}
int lms6002d_dev::general_dc_calibration_loop(uint8_t dc_addr, uint8_t calibration_reg_base)
{
uint8_t reg_val;

60
host/lms6002d.hpp
View File

@@ -461,66 +461,6 @@ public:
lms_clear_bits(0x70, (1 << 1));
}
/** Load value from 0x52/0x62 register to a selected DC calibration register */
void set_dc_calibration_value(uint8_t dc_addr, uint8_t calibration_reg_base, uint8_t value);
/** Get selected DC calibration register value */
uint8_t get_dc_calibration_value(uint8_t dc_addr, uint8_t calibration_reg_base);
/** Set value for the Rx FE DC calibration, I channel */
void set_rxfe_dc_i(int8_t value);
/** Get value for the Rx FE DC calibration, I channel */
int8_t get_rxfe_dc_i();
/** Set value for the Rx FE DC calibration, Q channel */
void set_rxfe_dc_q(int8_t value);
/** Get value for the Rx FE DC calibration, Q channel */
int8_t get_rxfe_dc_q();
/** Set value for the Rx LPF DC calibration, I channel */
void set_rxlpf_dc_i(uint8_t value);
/** Get value for the Rx LPF DC calibration, I channel */
uint8_t get_rxlpf_dc_i();
/** Set value for the Rx LPF DC calibration, Q channel */
void set_rxlpf_dc_q(uint8_t value);
/** Get value for the Rx LPF DC calibration, Q channel */
uint8_t get_rxlpf_dc_q();
/** Set value for the Rx VGA2 DC reference module */
void set_rxvga2_dc_reference(uint8_t value);
/** Get value for the Rx VGA2 DC reference module */
uint8_t get_rxvga2_dc_reference();
/** Set value for the Rx First gain stage (VGA2A), I channel */
void set_rxvga2a_dc_i(uint8_t value);
/** Get value for the Rx First gain stage (VGA2A), I channel */
uint8_t get_rxvga2a_dc_i();
/** Set value for the Rx First gain stage (VGA2A), Q channel */
void set_rxvga2a_dc_q(uint8_t value);
/** Get value for the Rx First gain stage (VGA2A), Q channel */
uint8_t get_rxvga2a_dc_q();
/** Set value for the Rx Second gain stage (VGA2B), I channel */
void set_rxvga2b_dc_i(uint8_t value);
/** Get value for the Rx Second gain stage (VGA2A), I channel */
uint8_t get_rxvga2b_dc_i();
/** Set value for the Rx Second gain stage (VGA2B), Q channel */
void set_rxvga2b_dc_q(uint8_t value);
/** Get value for the Rx Second gain stage (VGA2B), Q channel */
uint8_t get_rxvga2b_dc_q();
/** Programming and Calibration Guide: 4.1 General DC Calibration Procedure */
int general_dc_calibration_loop(uint8_t dc_addr, uint8_t calibration_reg_base);

303
host/lms6002d_ctrl.cpp
View File

@@ -131,7 +131,7 @@ public:
class lms6002d_ctrl_impl : public lms6002d_ctrl {
public:
lms6002d_ctrl_impl(uhd::spi_iface::sptr spiface, const int lms_spi_number, const double clock_rate);
lms6002d_ctrl_impl(uhd::spi_iface::sptr spiface, const int lms_spi_number, const int adf4350_spi_number, const double clock_rate);
double set_rx_freq(const double freq)
{
@@ -237,7 +237,19 @@ protected:
if (unit==dboard_iface::UNIT_TX) {
actual_freq = lms.tx_pll_tune(ref_freq, f);
} else if (unit==dboard_iface::UNIT_RX) {
#if 1
actual_freq = lms.rx_pll_tune(ref_freq, f);
#else
// New beta version of the code for UmSEL support.
const double umsel_if = 359.5e6;
double actual_lms_freq = lms.rx_pll_tune(ref_freq, umsel_if);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_freq() actual_lms_freq=%f\n", actual_lms_freq);
double adf4350_freq = f - actual_lms_freq;
actual_freq = tune_adf4350(adf4350_freq);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_freq() adf4350 freq=%f\n", actual_freq);
actual_freq += actual_lms_freq;
if (verbosity>0) printf("lms6002d_ctrl_impl::set_freq() actual_freq=%f\n", actual_freq);
#endif
} else {
assert(!"Wrong units_t value passed to lms6002d_ctrl_impl::set_freq()");
}
@@ -393,140 +405,207 @@ protected:
return offset;
}
void set_rxfe_dc_i(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxfe_dc_i(%d)\n", value);
lms.set_rxfe_dc_i(value);
}
uint8_t get_rxfe_dc_i() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxfe_dc_i()\n");
return lms.get_rxfe_dc_i();
}
void set_rxfe_dc_q(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxfe_dc_q(%d)\n", value);
lms.set_rxfe_dc_q(value);
}
uint8_t get_rxfe_dc_q() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxfe_dc_q()\n");
return lms.get_rxfe_dc_q();
}
void set_rxlpf_dc_i(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxlpf_dc_i(%d)\n", value);
lms.set_rxlpf_dc_i(value);
}
uint8_t get_rxlpf_dc_i() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxlpf_dc_i()\n");
return lms.get_rxlpf_dc_i();
}
void set_rxlpf_dc_q(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxlpf_dc_q(%d)\n", value);
lms.set_rxlpf_dc_q(value);
}
uint8_t get_rxlpf_dc_q() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxlpf_dc_q()\n");
return lms.get_rxlpf_dc_q();
}
void set_rxvga2_dc_reference(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxvga2_dc_reference(%d)\n", value);
lms.set_rxvga2_dc_reference(value);
}
uint8_t get_rxvga2_dc_reference() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxvga2_dc_reference()\n");
return lms.get_rxvga2_dc_reference();
}
void set_rxvga2a_dc_i(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxvga2a_dc_i(%d)\n", value);
lms.set_rxvga2a_dc_i(value);
}
uint8_t get_rxvga2a_dc_i() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxvga2a_dc_i()\n");
return lms.get_rxvga2a_dc_i();
}
void set_rxvga2a_dc_q(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxvga2a_dc_q(%d)\n", value);
lms.set_rxvga2a_dc_q(value);
}
uint8_t get_rxvga2a_dc_q() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxvga2a_dc_q()\n");
return lms.get_rxvga2a_dc_q();
}
void set_rxvga2b_dc_i(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxvga2b_dc_i(%d)\n", value);
lms.set_rxvga2b_dc_i(value);
}
uint8_t get_rxvga2b_dc_i() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxvga2b_dc_i()\n");
return lms.get_rxvga2b_dc_i();
}
void set_rxvga2b_dc_q(uint8_t value) {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::set_rxvga2b_dc_q(%d)\n", value);
lms.set_rxvga2b_dc_q(value);
}
uint8_t get_rxvga2b_dc_q() {
boost::recursive_mutex::scoped_lock l(_mutex);
if (verbosity>0) printf("lms6002d_ctrl_impl::get_rxvga2b_dc_q()\n");
return lms.get_rxvga2b_dc_q();
}
private:
umtrx_lms6002d_dev lms; // Interface to the LMS chip.
int tx_vga1gain, tx_vga2gain; // Stored values of Tx VGA1 and VGA2 gains.
bool rf_loopback_enabled; // Whether RF loopback is enabled.
// Tune ADF4350 on an UmSEL
double tune_adf4350(double target_freq);
uhd::spi_iface::sptr _spiface;
const int _lms_spi_number;
const int _adf4350_spi_number;
const double _clock_rate;
boost::recursive_mutex _mutex;
};
lms6002d_ctrl::sptr lms6002d_ctrl::make(uhd::spi_iface::sptr spiface, const int lms_spi_number, const double clock_rate)
lms6002d_ctrl::sptr lms6002d_ctrl::make(uhd::spi_iface::sptr spiface, const int lms_spi_number, const int adf4350_spi_number, const double clock_rate)
{
return sptr(new lms6002d_ctrl_impl(spiface, lms_spi_number, clock_rate));
return sptr(new lms6002d_ctrl_impl(spiface, lms_spi_number, adf4350_spi_number, clock_rate));
}
/***********************************************************************
* Tuning
**********************************************************************/
double lms6002d_ctrl_impl::tune_adf4350(double target_freq) {
UHD_LOGV(often) << boost::format(
"UmSEL tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
//clip the input
// TODO::::::::::::::::::::::::::::::::
// target_freq = sbx_freq_range.clip(target_freq);
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4350_regs_t::PRESCALER_4_5
(1,75) //adf4350_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4350_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4350_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4350_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4350_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4350_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4350_regs_t::RF_DIVIDER_SELECT_DIV16)
;
double actual_freq, pfd_freq;
// TODO:: May be *2? Check
double ref_freq = _clock_rate * 2;
int R=0, BS=0, N=0, FRAC=0, MOD=0;
int RFdiv = 1;
adf4350_regs_t::reference_divide_by_2_t T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
adf4350_regs_t::reference_doubler_t D = adf4350_regs_t::REFERENCE_DOUBLER_DISABLED;
//Reference doubler for 50% duty cycle
// if ref_freq < 12.5MHz enable regs.reference_divide_by_2
if(ref_freq <= 12.5e6) D = adf4350_regs_t::REFERENCE_DOUBLER_ENABLED;
//increase RF divider until acceptable VCO frequency
//start with target_freq*2 because mixer has divide by 2
double vco_freq = target_freq;
while (vco_freq < 2.2e9) {
vco_freq *= 2;
RFdiv *= 2;
}
//use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler)
adf4350_regs_t::prescaler_t prescaler = vco_freq > 3e9 ? adf4350_regs_t::PRESCALER_8_9 : adf4350_regs_t::PRESCALER_4_5;
/*
* The goal here is to loop though possible R dividers,
* band select clock dividers, N (int) dividers, and FRAC
* (frac) dividers.
*
* Calculate the N and F dividers for each set of values.
* The loop exists when it meets all of the constraints.
* The resulting loop values are loaded into the registers.
*
* from pg.21
*
* f_pfd = f_ref*(1+D)/(R*(1+T))
* f_vco = (N + (FRAC/MOD))*f_pfd
* N = f_vco/f_pfd - FRAC/MOD = f_vco*((R*(T+1))/(f_ref*(1+D))) - FRAC/MOD
* f_rf = f_vco/RFdiv)
* f_actual = f_rf/2
*/
for(R = 1; R <= 1023; R+=1){
//PFD input frequency = f_ref/R ... ignoring Reference doubler/divide-by-2 (D & T)
pfd_freq = ref_freq*(1+D)/(R*(1+T));
//keep the PFD frequency at or below 25MHz (Loop Filter Bandwidth)
if (pfd_freq > 25e6) continue;
//ignore fractional part of tuning
N = int(std::floor(vco_freq/pfd_freq));
//keep N > minimum int divider requirement
if (N < prescaler_to_min_int_div[prescaler]) continue;
for(BS=1; BS <= 255; BS+=1){
//keep the band select frequency at or below 100KHz
//constraint on band select clock
if (pfd_freq/BS > 100e3) continue;
goto done_loop;
}
} done_loop:
//Fractional-N calculation
MOD = 4095; //max fractional accuracy
FRAC = int((vco_freq/pfd_freq - N)*MOD);
//Reference divide-by-2 for 50% duty cycle
// if R even, move one divide by 2 to to regs.reference_divide_by_2
if(R % 2 == 0){
T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED;
R /= 2;
}
//actual frequency calculation
actual_freq = double((N + (double(FRAC)/double(MOD)))*ref_freq*(1+int(D))/(R*(1+int(T)))/RFdiv);
// TODO:: get_locked!
// UHD_LOGV(often)
std::cout
<< boost::format("UmSEL Intermediates: ref=%0.2f, outdiv=%f, fbdiv=%f") % (ref_freq*(1+int(D))/(R*(1+int(T)))) % double(RFdiv*2) % double(N + double(FRAC)/double(MOD)) << std::endl
<< boost::format("UmSEL tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d, LD=%s"
) % R % BS % N % FRAC % MOD % T % D % RFdiv % true /* this->get_locked(unit).to_pp_string() */ << std::endl
<< boost::format("UmSEL Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f"
) % (target_freq/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl;
//load the register values
adf4350_regs_t regs;
// TODO:: What?
// if ((unit == dboard_iface::UNIT_TX) and (actual_freq == sbx_tx_lo_2dbm.clip(actual_freq)))
// regs.output_power = adf4350_regs_t::OUTPUT_POWER_2DBM;
// else
regs.output_power = adf4350_regs_t::OUTPUT_POWER_5DBM;
regs.frac_12_bit = FRAC;
regs.int_16_bit = N;
regs.mod_12_bit = MOD;
regs.prescaler = prescaler;
regs.r_counter_10_bit = R;
regs.reference_divide_by_2 = T;
regs.reference_doubler = D;
regs.band_select_clock_div = BS;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv));
regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
regs.mute_till_lock_detect = adf4350_regs_t::MUTE_TILL_LOCK_DETECT_MUTE_ENABLED;
regs.charge_pump_current = adf4350_regs_t::CHARGE_PUMP_CURRENT_2_50MA;
regs.double_buffer = adf4350_regs_t::DOUBLE_BUFFER_ENABLED;
regs.muxout = adf4350_regs_t::MUXOUT_3STATE;
regs.low_noise_and_spur = adf4350_regs_t::LOW_NOISE_AND_SPUR_LOW_NOISE;
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
#if 0
for(addr=5; addr>=0; addr--){
// UHD_LOGV(often)
std::cout << boost::format(
"UmSEL SPI Reg (0x%02x): 0x%08x"
) % addr % regs.get_reg(addr) << std::endl;
this->get_iface()->write_spi(
uhd::usrp::dboard_iface::UNIT_SYNT, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
#else
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, 0x0580000|5, 32);
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, 0x0BFF4F8|4, 32);
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, 0x0040000|3, 32);
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, 0x1006E40|2, 32);
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, 0x8008208|1, 32);
_spiface->write_spi(_adf4350_spi_number, spi_config_t::EDGE_RISE, (325<<15)|(1<<3)|0, 32);
#endif
//return the actual frequency
// UHD_LOGV(often) << boost::format(
std::cout << boost::format(
"UmSEL tune: actual frequency %f Mhz"
) % (actual_freq/1e6) << std::endl;
return actual_freq;
}
// LMS RX dboard configuration
lms6002d_ctrl_impl::lms6002d_ctrl_impl(uhd::spi_iface::sptr spiface, const int lms_spi_number, const double clock_rate) :
lms6002d_ctrl_impl::lms6002d_ctrl_impl(uhd::spi_iface::sptr spiface, const int lms_spi_number, const int adf4350_spi_number, const double clock_rate) :
lms(umtrx_lms6002d_dev(spiface, lms_spi_number)),
tx_vga1gain(lms.get_tx_vga1gain()),
tx_vga2gain(lms.get_tx_vga2gain()),
rf_loopback_enabled(false),
_spiface(spiface),
_lms_spi_number(lms_spi_number),
_adf4350_spi_number(adf4350_spi_number),
_clock_rate(clock_rate)
{
////////////////////////////////////////////////////////////////////

21
host/lms6002d_ctrl.hpp
View File

@@ -15,7 +15,7 @@ class lms6002d_ctrl
{
public:
typedef boost::shared_ptr<lms6002d_ctrl> sptr;
static sptr make(uhd::spi_iface::sptr spiface, const int lms_spi_number, const double clock_rate);
static sptr make(uhd::spi_iface::sptr spiface, const int lms_spi_number, const int adf4350_spi_number, const double clock_rate);
virtual double set_rx_freq(const double freq) = 0;
virtual double set_tx_freq(const double freq) = 0;
@@ -55,25 +55,6 @@ public:
virtual uint8_t get_tx_vga1dc_i_int(void) = 0;
virtual uint8_t get_tx_vga1dc_q_int(void) = 0;
virtual void set_rxfe_dc_i(uint8_t value) = 0;
virtual uint8_t get_rxfe_dc_i() = 0;
virtual void set_rxfe_dc_q(uint8_t value) = 0;
virtual uint8_t get_rxfe_dc_q() = 0;
virtual void set_rxlpf_dc_i(uint8_t value) = 0;
virtual uint8_t get_rxlpf_dc_i() = 0;
virtual void set_rxlpf_dc_q(uint8_t value) = 0;
virtual uint8_t get_rxlpf_dc_q() = 0;
virtual void set_rxvga2_dc_reference(uint8_t value) = 0;
virtual uint8_t get_rxvga2_dc_reference() = 0;
virtual void set_rxvga2a_dc_i(uint8_t value) = 0;
virtual uint8_t get_rxvga2a_dc_i() = 0;
virtual void set_rxvga2a_dc_q(uint8_t value) = 0;
virtual uint8_t get_rxvga2a_dc_q() = 0;
virtual void set_rxvga2b_dc_i(uint8_t value) = 0;
virtual uint8_t get_rxvga2b_dc_i() = 0;
virtual void set_rxvga2b_dc_q(uint8_t value) = 0;
virtual uint8_t get_rxvga2b_dc_q() = 0;
};
#endif /* INCLUDED_LMS6002D_CTRL_HPP */

478
host/umsel2_ctrl.cpp
View File

@@ -1,478 +0,0 @@
// Copyright 2015-2015 Fairwaves LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#include "umsel2_ctrl.hpp"
#include "umtrx_regs.hpp"
#include <uhd/exception.hpp>
#include <boost/thread.hpp>
#include <iostream>
#include <cmath>
#include <map>
static const int REG0_NVALUE_SHIFT = 4;
static const int REG0_NVALUE_MASK = 0xffff;
static const int REG0_PRESCALER_SHIFT = 20;
static const int REG0_AUTOCAL_SHIFT = 21;
static const int REG1_MFRAC_SHIFT = 4;
static const int REG1_MFRAC_MASK = 0xffffff;
static const int REG2_AUX_FRAC_SHIFT = 18;
static const int REG2_AUX_FRAC_MASK = ((1<<14)-1);
static const int REG2_AUX_MOD_SHIFT = 4;
static const int REG2_AUX_MOD_MASK = ((1<<14)-1);
static const int REG3_SD_LOAD_SHIFT = 30;
static const int REG3_PHASE_RSYNC_SHIFT = 29;
static const int REG3_PHASE_ADJ_SHIFT = 28;
static const int REG3_PHASE_SHIFT = 4;
static const int REG3_PHASE_MASK = ((1<<24)-1);
static const int REG4_MUXOUT_SHIFT = 27;
static const int REG4_MUXOUT_MASK = ((1<<3)-1);
static const int REG4_REF_DBL_SHIFT = 26;
static const int REG4_REF_DIV_SHIFT = 25;
static const int REG4_R_SHIFT = 15;
static const int REG4_R_MASK = ((1<<10)-1);
static const int REG4_DBL_BUFF_SHIFT = 14;
static const int REG4_CURRENT_SHIFT = 10;
static const int REG4_CURRENT_MASK = ((1<<4)-1);
static const int REG4_REF_MODE_SHIFT = 9;
static const int REG4_MUX_LOGIC_SHIFT = 8;
static const int REG4_PD_POL_SHIFT = 7;
static const int REG4_PWR_DOWN_SHIFT = 6;
static const int REG4_CP_3STATE_SHIFT = 5;
static const int REG4_CNTR_RESET = 4;
static const int REG5_RESERVED = 0x00800025;
static const int REG6_GATED_BLEED_SHIFT = 30;
static const int REG6_NEG_BLEED_SHIFT = 29;
static const int REG6_RESERVED_SHIFT = 25;
static const int REG6_RESERVED_VALUE = 0xA;
static const int REG6_FB_SEL_SHIFT = 24;
static const int REG6_RF_DIV_SHIFT = 21;
static const int REG6_RF_DIV_MASK = ((1<<3)-1);
static const int REG6_CP_BLEED_CURR_SHIFT = 13;
static const int REG6_CP_BLEED_CURR_MASK = ((1<<8)-1);
static const int REG6_MLTD_SHIFT = 11;
static const int REG6_AUX_PWR_EN_SHIFT = 9;
static const int REG6_AUX_PWR_SHIFT = 7;
static const int REG6_AUX_PWR_MASK = ((1<<2)-1);
static const int REG6_PWR_EN_SHIFT = 6;
static const int REG6_PWR_SHIFT = 4;
static const int REG6_PWR_MASK = ((1<<2)-1);
static const int REG7_RESERVED_SHIFT = 26;
static const int REG7_RESERVED_VALUE = 0x4;
static const int REG7_LE_SYNC_SHIFT = 25;
static const int REG7_LD_CYCLE_CNT_SHIFT = 8;
static const int REG7_LD_CYCLE_CNT_MASK = ((1<<2)-1);
static const int REG7_LOL_MODE_SHIFT = 7;
static const int REG7_FRAC_N_PREC_SHIFT = 5;
static const int REG7_FRAC_N_PREC_MASK = ((1<<2)-1);
static const int REG7_LD_MODE_SHIFT = 4;
static const int REG8_RESERVED = 0x102D0428;
static const int REG9_VCO_BAND_SHIFT = 24;
static const int REG9_VCO_BAND_MASK = ((1<<8)-1);
static const int REG9_TIMEOUT_SHIFT = 14;
static const int REG9_TIMEOUT_MASK = ((1<<10)-1);
static const int REG9_AUTO_LVL_TO_SHIFT = 9;
static const int REG9_AUTO_LVL_TO_MASK = ((1<<5)-1);
static const int REG9_SYNT_LOCK_TO_SHIFT = 4;
static const int REG9_SYNT_LOCK_TO_MASK = ((1<<5)-1);
static const int REG10_RESERVED_SHIFT = 14;
static const int REG10_RESERVED_VALUE = 0x300;
static const int REG10_ADC_CLK_DIV_SHIFT = 6;
static const int REG10_ADC_CLK_DIV_MASK = ((1<<8)-1);
static const int REG10_ADC_CONV_SHIFT = 5;
static const int REG10_ADC_EN_SHIFT = 4;
static const int REG11_RESERVED = 0x0061300B;
static const int REG12_RESYNC_CLOCK_SHIFT = 16;
static const int REG12_RESYNC_CLOCK_MASK = ((1<<16)-1);
static const int REG12_RESERVED_SHIFT = 4;
static const int REG12_RESERVED_VALUE = 0x41;
#define MODIFY_FIELD(reg, val, mask, shift) \
reg = ((reg & ~(mask << shift)) | ((val & mask) << shift))
class umsel2_ctrl_impl : public umsel2_ctrl
{
public:
umsel2_ctrl_impl(uhd::wb_iface::sptr ctrl, uhd::spi_iface::sptr spiface, const double ref_clock, const bool verbose):
_ctrl(ctrl), _spiface(spiface), _ref_clock(ref_clock), verbose(verbose)
{
this->init_synth(SPI_SS_AUX1);
this->init_synth(SPI_SS_AUX2);
//--------- basic self tests, use the muxout to verify communication ----------//
//set mux out to ground in both cases
MODIFY_FIELD(_regs[SPI_SS_AUX1][4], 2, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
MODIFY_FIELD(_regs[SPI_SS_AUX2][4], 2, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
this->write_reg(SPI_SS_AUX1, 4);
this->write_reg(SPI_SS_AUX2, 4);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD1_IRQ_BIT) == 0);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD2_IRQ_BIT) == 0);
//set slave1 to muxout vdd
MODIFY_FIELD(_regs[SPI_SS_AUX1][4], 1, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
MODIFY_FIELD(_regs[SPI_SS_AUX2][4], 2, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
this->write_reg(SPI_SS_AUX1, 4);
this->write_reg(SPI_SS_AUX2, 4);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD1_IRQ_BIT) != 0);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD2_IRQ_BIT) == 0);
//set slave2 to muxout vdd
MODIFY_FIELD(_regs[SPI_SS_AUX1][4], 2, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
MODIFY_FIELD(_regs[SPI_SS_AUX2][4], 1, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
this->write_reg(SPI_SS_AUX1, 4);
this->write_reg(SPI_SS_AUX2, 4);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD1_IRQ_BIT) == 0);
UHD_ASSERT_THROW((_ctrl->peek32(U2_REG_IRQ_RB) & AUX_LD2_IRQ_BIT) != 0);
//restore lock detect out
MODIFY_FIELD(_regs[SPI_SS_AUX1][4], 6, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
MODIFY_FIELD(_regs[SPI_SS_AUX2][4], 6, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
this->write_reg(SPI_SS_AUX1, 4);
this->write_reg(SPI_SS_AUX2, 4);
}
~umsel2_ctrl_impl(void)
{
try
{
this->pd_synth(SPI_SS_AUX1);
this->pd_synth(SPI_SS_AUX2);
}
catch(...){}
}
uhd::freq_range_t get_rx_freq_range(const int)
{
return uhd::freq_range_t(54e6, 4400e6);
}
double set_rx_freq(const int which, const double freq)
{
const int slaveno = (which == 1)?SPI_SS_AUX1 : SPI_SS_AUX2;
return this->tune_synth(slaveno, freq);
}
uhd::sensor_value_t get_locked(const int which)
{
boost::uint32_t irq = _ctrl->peek32(U2_REG_IRQ_RB);
bool locked = false;
if (which == 1) locked = (irq & AUX_LD1_IRQ_BIT) != 0;
if (which == 2) locked = (irq & AUX_LD2_IRQ_BIT) != 0;
return uhd::sensor_value_t("LO", locked, "locked", "unlocked");
}
private:
void init_synth(const int slaveno)
{
//reset the registers
_regs[slaveno][0] = 0;
_regs[slaveno][1] = 0;
_regs[slaveno][2] = 0;
_regs[slaveno][3] = 0;
_regs[slaveno][4] = 0;
_regs[slaveno][5] = REG5_RESERVED;
_regs[slaveno][6] = REG6_RESERVED_VALUE << REG6_RESERVED_SHIFT;
_regs[slaveno][7] = REG7_RESERVED_VALUE << REG7_RESERVED_SHIFT;
_regs[slaveno][8] = REG8_RESERVED;
_regs[slaveno][9] = 0;
_regs[slaveno][10] = REG10_RESERVED_VALUE << REG10_RESERVED_SHIFT;
_regs[slaveno][11] = REG11_RESERVED;
_regs[slaveno][12] = REG12_RESERVED_VALUE << REG12_RESERVED_SHIFT;
//------------------------------------------------------------//
//----------------------- register 0 -------------------------//
//------------------------------------------------------------//
//autocal enabled
MODIFY_FIELD(_regs[slaveno][0], 1, 0x1, REG0_AUTOCAL_SHIFT);
//prescaler 4/5
MODIFY_FIELD(_regs[slaveno][0], 0, 0x1, REG0_PRESCALER_SHIFT);
//------------------------------------------------------------//
//----------------------- register 3 -------------------------//
//------------------------------------------------------------//
//sd load reset, phase resync, phase adjust = disabled
MODIFY_FIELD(_regs[slaveno][3], 0, 0x1, REG3_SD_LOAD_SHIFT);
MODIFY_FIELD(_regs[slaveno][3], 0, 0x1, REG3_PHASE_RSYNC_SHIFT);
MODIFY_FIELD(_regs[slaveno][3], 0, 0x1, REG3_PHASE_ADJ_SHIFT);
MODIFY_FIELD(_regs[slaveno][3], 0, REG3_PHASE_MASK, REG3_PHASE_SHIFT);
//------------------------------------------------------------//
//----------------------- register 4 -------------------------//
//------------------------------------------------------------//
//muxout to lock detect
MODIFY_FIELD(_regs[slaveno][4], 6, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
//double buff disabled
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_DBL_BUFF_SHIFT);
//charge pump current 0.31mA@5.1k
MODIFY_FIELD(_regs[slaveno][4], 0, REG4_CURRENT_MASK, REG4_CURRENT_SHIFT);
//refin single ended
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_REF_MODE_SHIFT);
//mux level 3V
MODIFY_FIELD(_regs[slaveno][4], 1, 0x1, REG4_MUX_LOGIC_SHIFT);
//PD polarity positive
MODIFY_FIELD(_regs[slaveno][4], 1, 0x1, REG4_PD_POL_SHIFT);
//power down disabled
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_PWR_DOWN_SHIFT);
//charge-pump 3-state disabled
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_CP_3STATE_SHIFT);
//counter reset disabled
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_CNTR_RESET);
//------------------------------------------------------------//
//----------------------- register 6 -------------------------//
//------------------------------------------------------------//
//feedback fundamental
MODIFY_FIELD(_regs[slaveno][6], 1, 0x1, REG6_FB_SEL_SHIFT);
//bleed current 7.5uA
MODIFY_FIELD(_regs[slaveno][6], 2, REG6_CP_BLEED_CURR_MASK, REG6_CP_BLEED_CURR_SHIFT);
//mute until lock detect disabled
MODIFY_FIELD(_regs[slaveno][6], 0, 0x1, REG6_MLTD_SHIFT);
//aux output disabled (-1dBm)
MODIFY_FIELD(_regs[slaveno][6], 0, 0x1, REG6_AUX_PWR_EN_SHIFT);
MODIFY_FIELD(_regs[slaveno][6], 1, REG6_AUX_PWR_MASK, REG6_AUX_PWR_SHIFT);
//RF output power (5dBm)
MODIFY_FIELD(_regs[slaveno][6], 1, 0x1, REG6_PWR_EN_SHIFT);
MODIFY_FIELD(_regs[slaveno][6], 3, REG6_PWR_MASK, REG6_PWR_SHIFT);
//negative bleed enabled
MODIFY_FIELD(_regs[slaveno][6], 1, 0x1, REG6_NEG_BLEED_SHIFT);
//gated bleed disabled
MODIFY_FIELD(_regs[slaveno][6], 0, 0x1, REG6_GATED_BLEED_SHIFT);
//------------------------------------------------------------//
//----------------------- register 7 -------------------------//
//------------------------------------------------------------//
//LE Sync REFin
MODIFY_FIELD(_regs[slaveno][7], 1, 0x1, REG7_LE_SYNC_SHIFT);
//LD Cycles
MODIFY_FIELD(_regs[slaveno][7], 1024, REG7_LD_CYCLE_CNT_MASK, REG7_LD_CYCLE_CNT_SHIFT);
//LOL Mode disabled
MODIFY_FIELD(_regs[slaveno][7], 0, 0x1, REG7_LOL_MODE_SHIFT);
//Frac-N LD Prec 5.0ns
MODIFY_FIELD(_regs[slaveno][7], 0, REG7_FRAC_N_PREC_MASK, REG7_FRAC_N_PREC_SHIFT);
//LD Mode Frac-N
MODIFY_FIELD(_regs[slaveno][7], 0, 0x1, REG7_LD_MODE_SHIFT);
//------------------------------------------------------------//
//----------------------- register 10 ------------------------//
//------------------------------------------------------------//
//adc enable
MODIFY_FIELD(_regs[slaveno][10], 1, 0x1, REG10_ADC_EN_SHIFT);
//adc conversion enable
MODIFY_FIELD(_regs[slaveno][10], 1, 0x1, REG10_ADC_CONV_SHIFT);
//------------------------------------------------------------//
//----------------------- register 12 ------------------------//
//------------------------------------------------------------//
//phase resync 0
MODIFY_FIELD(_regs[slaveno][12], 0, REG12_RESYNC_CLOCK_MASK, REG12_RESYNC_CLOCK_SHIFT);
//write all registers
for (int addr = 12; addr >= 0; addr--)
this->write_reg(slaveno, addr);
}
void pd_synth(const int slaveno)
{
//muxout to lock 3state
MODIFY_FIELD(_regs[slaveno][4], 0, REG4_MUXOUT_MASK, REG4_MUXOUT_SHIFT);
//charge pump 3state
MODIFY_FIELD(_regs[slaveno][4], 1, 0x1, REG4_CP_3STATE_SHIFT);
//power down
MODIFY_FIELD(_regs[slaveno][4], 1, 0x1, REG4_PWR_DOWN_SHIFT);
//outputs off
MODIFY_FIELD(_regs[slaveno][6], 0, 0x1, REG6_AUX_PWR_EN_SHIFT);
MODIFY_FIELD(_regs[slaveno][6], 0, 0x1, REG6_PWR_EN_SHIFT);
//write all registers
for (int addr = 12; addr >= 0; addr--)
this->write_reg(slaveno, addr);
}
double tune_synth(const int slaveno, const double RFout)
{
if (verbose) std::cout << " tune_synth(slaveno=" << slaveno << ")" << std::endl;
if (verbose) std::cout << " RFout " << (RFout/1e6) << " MHz" << std::endl;
//determine the reference out divider and VCOout
double VCOout = 0;
int RFOUTDIVSEL = 0;
while (true)
{
int RFOUTDIV = 1 << RFOUTDIVSEL;
VCOout = RFout*RFOUTDIV;
if (VCOout < 3.4e9) RFOUTDIVSEL++;
else break;
}
if (verbose) std::cout << " RFOUTDIV " << (1 << RFOUTDIVSEL) << "" << std::endl;
if (verbose) std::cout << " VCOout " << (VCOout/1e6) << " MHz" << std::endl;
//use doubler to increase the pfd frequency (good for noise performance)
int REFDBL = 0;
int REFDIV = 0;
//prescaler settings
int PRESCALER = 0; //4/5
const int Nmin = (PRESCALER==0)?23:75;
//calculate the R divider, N divider, and PDF frequency
double NDIV = 0;
int RDIV = 1;
double fPFD = 0;
while (true)
{
fPFD = _ref_clock*(double(1+REFDBL)/double(RDIV*(1+REFDIV)));
NDIV = VCOout/fPFD;
if (NDIV < Nmin) RDIV++;
else break;
}
if (verbose) std::cout << " RDIV " << RDIV << "" << std::endl;
if (verbose) std::cout << " NDIV " << NDIV << "" << std::endl;
if (verbose) std::cout << " fPFD " << (fPFD/1e6) << " MHz" << std::endl;
//calculate the integer parts of the N divider
int NINT = int(NDIV);
double NFRAC = std::ldexp(NDIV-NINT, 24);
int FRAC1 = int(NFRAC);
int MOD2 = fPFD/1e6; //TODO MOD2 = fPFD/GCD(fPFD, fCHSP)
int FRAC2 = int((NFRAC-FRAC1)*MOD2);
if (verbose) std::cout << " NINT " << NINT << "" << std::endl;
if (verbose) std::cout << " FRAC1 " << FRAC1 << "" << std::endl;
if (verbose) std::cout << " MOD2 " << MOD2 << "" << std::endl;
if (verbose) std::cout << " FRAC2 " << FRAC2 << "" << std::endl;
//VCO Band Division
//PFD/(band division × 16) < 150 kHz
int VCObanddiv = 1;
while (not(fPFD/(VCObanddiv*16) < 150e3)) VCObanddiv++;
if (verbose) std::cout << " VCObanddiv " << VCObanddiv << "" << std::endl;
//Maximize ALC Wait (to reduce Timeout to minimize time) so
//that ALC Wait = 30 and Synthesizer Lock Timeout = 12.
int ALC = 30;
int SLT = 12;
int TIMEOUT = std::ceil((fPFD*50e-6)/ALC);
if (verbose) std::cout << " TIMEOUT " << TIMEOUT << "" << std::endl;
//ADC Clock Divider (ADC_CLK_DIV)
//PFD/((ADC_CLK_DIV × 4) × 2) < 100 kHz
/*
int ADC_CLK_DIV = 1;
while (not(fPFD/((ADC_CLK_DIV*4)*2) < 100e3)) ADC_CLK_DIV++;
if (verbose) std::cout << " ADC_CLK_DIV " << ADC_CLK_DIV << "" << std::endl;
const long sleepUs = long(1e6*16*ADC_CLK_DIV/fPFD);
*/
//Copied from the ADI GUI
//after trying to juxtapose the documentation with the GUI
int ADC_CLK_DIV = 65;
const long sleepUs = 160;
//load registers
MODIFY_FIELD(_regs[slaveno][0], NINT, REG0_NVALUE_MASK, REG0_NVALUE_SHIFT);
MODIFY_FIELD(_regs[slaveno][0], PRESCALER, 0x1, REG0_PRESCALER_SHIFT);
MODIFY_FIELD(_regs[slaveno][0], 1/*enb*/, 0x1, REG0_AUTOCAL_SHIFT);
MODIFY_FIELD(_regs[slaveno][1], FRAC1, REG1_MFRAC_MASK, REG1_MFRAC_SHIFT);
MODIFY_FIELD(_regs[slaveno][2], MOD2, REG2_AUX_MOD_MASK, REG2_AUX_MOD_SHIFT);
MODIFY_FIELD(_regs[slaveno][2], FRAC2, REG2_AUX_FRAC_MASK, REG2_AUX_FRAC_SHIFT);
MODIFY_FIELD(_regs[slaveno][4], RDIV, REG4_R_MASK, REG4_R_SHIFT);
MODIFY_FIELD(_regs[slaveno][4], REFDIV, 0x1, REG4_REF_DIV_SHIFT);
MODIFY_FIELD(_regs[slaveno][4], REFDBL, 0x1, REG4_REF_DBL_SHIFT);
MODIFY_FIELD(_regs[slaveno][6], RFOUTDIVSEL, REG6_RF_DIV_MASK, REG6_RF_DIV_SHIFT);
MODIFY_FIELD(_regs[slaveno][9], SLT, REG9_SYNT_LOCK_TO_MASK, REG9_SYNT_LOCK_TO_SHIFT);
MODIFY_FIELD(_regs[slaveno][9], ALC, REG9_AUTO_LVL_TO_MASK, REG9_AUTO_LVL_TO_SHIFT);
MODIFY_FIELD(_regs[slaveno][9], TIMEOUT, REG9_TIMEOUT_MASK, REG9_TIMEOUT_SHIFT);
MODIFY_FIELD(_regs[slaveno][9], VCObanddiv, REG9_VCO_BAND_MASK, REG9_VCO_BAND_SHIFT);
MODIFY_FIELD(_regs[slaveno][10], ADC_CLK_DIV, REG10_ADC_CLK_DIV_MASK, REG10_ADC_CLK_DIV_SHIFT);
//write other registers
this->write_reg(slaveno, 6);
this->write_reg(slaveno, 9);
this->write_reg(slaveno, 10);
//FREQUENCY UPDATE SEQUENCE
MODIFY_FIELD(_regs[slaveno][4], 1, 0x1, REG4_CNTR_RESET);
this->write_reg(slaveno, 4);
this->write_reg(slaveno, 2);
this->write_reg(slaveno, 1);
MODIFY_FIELD(_regs[slaveno][0], 0, 0x1, REG0_AUTOCAL_SHIFT);
this->write_reg(slaveno, 0);
MODIFY_FIELD(_regs[slaveno][4], 0, 0x1, REG4_CNTR_RESET);
this->write_reg(slaveno, 4);
boost::this_thread::sleep(boost::posix_time::microseconds(sleepUs));
if (verbose) std::cout << " sleep time " << (sleepUs) << " us" << std::endl;
MODIFY_FIELD(_regs[slaveno][0], 1, 0x1, REG0_AUTOCAL_SHIFT);
this->write_reg(slaveno, 0);
//calculate actual tune value
double Nactual = NINT + std::ldexp(double(FRAC1 + FRAC2/double(MOD2)), -24);
double RFoutactual = (fPFD*Nactual)/(1 << RFOUTDIVSEL);
if (verbose) std::cout << " Nactual " << Nactual << "" << std::endl;
if (verbose) std::cout << " RFoutactual " << (RFoutactual/1e6) << " MHz" << std::endl;
if (verbose) boost::this_thread::sleep(boost::posix_time::microseconds(10000));
if (verbose) std::cout << " Locked " << this->get_locked((slaveno==SPI_SS_AUX1)?1:2).value << "" << std::endl;
return RFoutactual;
}
void write_reg(const int slaveno, const int addr)
{
int value = (_regs[slaveno][addr] & ~0xf) | addr;
if (verbose) std::cout << "write_reg[" << addr << "] = 0x" << std::hex << value << std::dec << std::endl;
_spiface->write_spi(slaveno, uhd::spi_config_t::EDGE_RISE, value, 32);
}
uhd::wb_iface::sptr _ctrl;
uhd::spi_iface::sptr _spiface;
const double _ref_clock;
std::map<int, std::map<int, int> > _regs;
const bool verbose;
};
umsel2_ctrl::sptr umsel2_ctrl::make(uhd::wb_iface::sptr ctrl, uhd::spi_iface::sptr spiface, const double ref_clock, const bool verbose)
{
return umsel2_ctrl::sptr(new umsel2_ctrl_impl(ctrl, spiface, ref_clock, verbose));
}

61
host/umsel2_ctrl.hpp
View File

@@ -1,61 +0,0 @@
// Copyright 2015-2015 Fairwaves LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
#ifndef INCLUDED_UMSEL2_CTRL_HPP
#define INCLUDED_UMSEL2_CTRL_HPP
#include <uhd/types/serial.hpp>
#include <uhd/types/wb_iface.hpp>
#include <uhd/types/sensors.hpp>
#include <uhd/types/ranges.hpp>
#include <boost/shared_ptr.hpp>
#include <boost/utility.hpp>
#define UMSEL2_CH1_LMS_IF 360e6
#define UMSEL2_CH2_LMS_IF 400e6
/*!
* Control UmSEL2 board.
*/
class umsel2_ctrl
{
public:
typedef boost::shared_ptr<umsel2_ctrl> sptr;
static sptr make(uhd::wb_iface::sptr ctrl, uhd::spi_iface::sptr spiface, const double ref_clock, const bool verbose);
/*!
* Query the tune range.
* \param which values 1 or 2
*/
virtual uhd::freq_range_t get_rx_freq_range(const int which) = 0;
/*!
* Tune the synthesizer
* \param which values 1 or 2
* \param freq the freq in Hz
* \return the actual freq in Hz
*/
virtual double set_rx_freq(const int which, const double freq) = 0;
/*!
* Query lock detect.
* \param which values 1 or 2
*/
virtual uhd::sensor_value_t get_locked(const int which) = 0;
};
#endif /* INCLUDED_UMSEL2_CTRL_HPP */

79
host/umtrx_fifo_ctrl.cpp
View File

@@ -29,11 +29,16 @@
using namespace uhd;
using namespace uhd::transport;
//command policy flags
static const size_t POKE32_CMD = (1 << 8);
static const size_t PEEK32_CMD = 0;
static const size_t PEEK32_CMD = 0; //no flag set
static const size_t TIME_WAIT_CMD = (1 << 9);
static const size_t SKIP_LATE_CMD = (1 << 10);
static const double ACK_TIMEOUT = 0.5;
static const double MASSIVE_TIMEOUT = 10.0; //for when we wait on a timed command
static const boost::uint32_t MAX_SEQS_OUT = 15;
static const boost::uint32_t FIFO_DEPTH = 64;
static const boost::uint32_t MAX_SEQS_OUT = FIFO_DEPTH-1;
#define SPI_DIV SR_SPI_CORE + 0
#define SPI_CTRL SR_SPI_CORE + 1
@@ -50,6 +55,12 @@ public:
_window_size(std::min(window_size, MAX_SEQS_OUT)),
_seq_out(0),
_seq_ack(0),
_prev_recv_seq(0),
_total_recv_packets(0),
_start_of_burst(false),
_skip_late(false),
_use_time(false),
_tick_rate(1.0),
_timeout(ACK_TIMEOUT)
{
UHD_MSG(status) << "fifo_ctrl.window_size = " << _window_size << std::endl;
@@ -155,6 +166,7 @@ public:
_time = time;
_use_time = _time != uhd::time_spec_t(0.0);
if (_use_time) _timeout = MASSIVE_TIMEOUT; //permanently sets larger timeout
_start_of_burst = true;
}
void set_tick_rate(const double rate){
@@ -162,6 +174,11 @@ public:
_tick_rate = rate;
}
void set_late_policy(const bool skip_late)
{
_skip_late = skip_late;
}
private:
/*******************************************************************
@@ -184,7 +201,8 @@ private:
packet_info.packet_count = _seq_out;
packet_info.sid = _sid;
packet_info.tsf = _time.to_ticks(_tick_rate);
packet_info.sob = false;
packet_info.sob = _start_of_burst;
_start_of_burst = false; //only set once by set time, then cleared
packet_info.eob = false;
packet_info.has_sid = true;
packet_info.has_cid = false;
@@ -195,6 +213,10 @@ private:
//load header
vrt::if_hdr_pack_be(pkt, packet_info);
//time command flags
if (_skip_late) cmd |= SKIP_LATE_CMD;
if (_use_time) cmd |= TIME_WAIT_CMD;
//load payload
const boost::uint32_t ctrl_word = (addr & 0xff) | cmd | (_seq_out << 16);
pkt[packet_info.num_header_words32+0] = htonl(ctrl_word);
@@ -221,10 +243,50 @@ private:
vrt::if_packet_info_t packet_info;
packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
vrt::if_hdr_unpack_be(pkt, packet_info);
_seq_ack = ntohl(pkt[packet_info.num_header_words32+0]) >> 16;
if (_seq_ack == seq_to_ack){
return ntohl(pkt[packet_info.num_header_words32+1]);
//extract the payloads
const boost::int32_t header = ntohl(pkt[packet_info.num_header_words32+0]);
const boost::int32_t rb_data = ntohl(pkt[packet_info.num_header_words32+1]);
const boost::int32_t last_header = ntohl(pkt[packet_info.num_header_words32+2]);
const boost::int32_t fifo_occupied = ntohl(pkt[packet_info.num_header_words32+3]);
const boost::uint16_t this_seq = header >> 16;
const boost::uint16_t last_seq = last_header >> 16;
const boost::uint16_t result_fifo_occupied = fifo_occupied >> 16;
const boost::uint16_t command_fifo_occupied = fifo_occupied & 0xffff;
//check if we lost packets from device -> host
const boost::uint16_t next_recv_seq = _prev_recv_seq+1;
if (next_recv_seq != this_seq)
{
UHD_MSG(error) << boost::format(
"Detected packet loss from device to host:\n"
"Host expected sequence 0x%x, but got 0x%x"
) % next_recv_seq % this_seq << std::endl;
}
//check if we lost packets from host -> device
if (_total_recv_packets != 0 and _prev_recv_seq != last_seq)
{
UHD_MSG(error) << boost::format(
"Detected packet loss from host to device:\n"
"Device expected last sequence 0x%x, but saw 0x%x"
) % _prev_recv_seq % last_seq << std::endl;
}
if (result_fifo_occupied > FIFO_DEPTH/2 or command_fifo_occupied > FIFO_DEPTH/2)
{
UHD_MSG(warning) << boost::format(
"FIFOs are past half capacity!\n"
"Command FIFO occupancy: %d/%d\n"
"Result FIFO occupancy: %d/%d"
) % command_fifo_occupied % FIFO_DEPTH % result_fifo_occupied % FIFO_DEPTH << std::endl;
}
//store state for next recv iteration
_total_recv_packets++;
_prev_recv_seq = this_seq;
_seq_ack = this_seq;
if (_seq_ack == seq_to_ack) return rb_data;
}
return 0;
@@ -236,7 +298,12 @@ private:
boost::mutex _mutex;
boost::uint16_t _seq_out;
boost::uint16_t _seq_ack;
boost::uint16_t _prev_recv_seq;
boost::uint16_t _next_recv_seq;
boost::uint64_t _total_recv_packets;
uhd::time_spec_t _time;
bool _start_of_burst;
bool _skip_late;
bool _use_time;
double _tick_rate;
double _timeout;

1
host/umtrx_fifo_ctrl.hpp
View File

@@ -23,7 +23,6 @@
#include <uhd/transport/zero_copy.hpp>
#include <boost/shared_ptr.hpp>
#include <boost/utility.hpp>
#include <boost/cstdint.hpp>
#include <uhd/types/wb_iface.hpp>
#include <string>

19
host/umtrx_iface.cpp
View File

@@ -70,16 +70,21 @@ public:
umtrx_iface_impl(udp_simple::sptr ctrl_transport):
_ctrl_transport(ctrl_transport),
_ctrl_seq_num(0),
_protocol_compat(USRP2_FW_COMPAT_NUM)
_protocol_compat(0) //initialized below...
{
//Obtain the firmware's compat number.
//Save the response compat number for communication.
//TODO can choose to reject certain older compat numbers
usrp2_ctrl_data_t ctrl_data;
ctrl_data.id = htonl(UMTRX_CTRL_ID_REQUEST);
ctrl_data = ctrl_send_and_recv(ctrl_data, _protocol_compat, ~0);
if (ntohl(ctrl_data.id) != UMTRX_CTRL_ID_RESPONSE)
throw uhd::runtime_error(str(boost::format("unexpected firmware response: -->%c<--") % (char)ntohl(ctrl_data.id)));
ctrl_data.id = htonl(USRP2_CTRL_ID_WAZZUP_BRO);
ctrl_data = ctrl_send_and_recv(ctrl_data, 0, ~0);
if (ntohl(ctrl_data.id) != USRP2_CTRL_ID_WAZZUP_DUDE) {
ctrl_data.id = htonl(UMTRX_CTRL_ID_REQUEST);
ctrl_data = ctrl_send_and_recv(ctrl_data, 0, ~0);
if (ntohl(ctrl_data.id) != UMTRX_CTRL_ID_RESPONSE)
throw uhd::runtime_error(str(boost::format("unexpected firmware response: -->%c<--") % (char)ntohl(ctrl_data.id)));
}
//Save the response compat number for future communication.
_protocol_compat = ntohl(ctrl_data.proto_ver);
// Read EEPROM with UMTRX extensions
@@ -316,7 +321,7 @@ public:
if(len >= sizeof(boost::uint32_t) and (hi < compat or lo > compat)){
throw uhd::runtime_error(str(boost::format(
"\nPlease update the firmware and FPGA images for your device.\n"
"See the application notes for UmTRX for instructions.\n"
"See the application notes for USRP2/N-Series for instructions.\n"
"Expected protocol compatibility number %s, but got %d:\n"
"The firmware build is not compatible with the host code build."
) % ((lo == hi)? (boost::format("%d") % hi) : (boost::format("[%d to %d]") % lo % hi)) % compat));

202
host/umtrx_impl.cpp
View File

@@ -38,9 +38,8 @@ const int umtrx_impl::UMTRX_VGA1_DEF = -20;
const int umtrx_impl::UMTRX_VGA2_DEF = 22;
const int umtrx_impl::UMTRX_VGA2_MIN = 0;
const double umtrx_impl::_dcdc_val_to_volt[umtrx_impl::DCDC_VER_COUNT][256] =
static const double _dcdc_val_to_volt_init[256] =
{
{
9.38, 9.38, 9.40, 9.42, 9.42, 9.44, 9.46, 9.46, 9.48, 9.50, // 10
9.50, 9.52, 9.54, 9.54, 9.56, 9.58, 9.58, 9.60, 9.60, 9.62, // 20
9.64, 9.66, 9.66, 9.68, 9.70, 9.70, 9.72, 9.74, 9.76, 9.76, // 30
@@ -67,35 +66,8 @@ const double umtrx_impl::_dcdc_val_to_volt[umtrx_impl::DCDC_VER_COUNT][256] =
20.02, 20.20, 20.38, 20.58, 20.76, 20.96, 21.18, 21.38, 21.60, 21.82, // 240
21.92, 22.16, 22.40, 22.66, 22.92, 23.18, 23.46, 23.74, 24.02, 24.30, // 250
24.62, 24.94, 25.28, 25.62, 25.98, 26.34
},{
4.84, 4.84, 4.86, 4.88, 4.88, 4.90, 4.92, 4.94, 4.94, 4.96, // 10
4.98, 5.00, 5.02, 5.02, 5.04, 5.06, 5.06, 5.08, 5.10, 5.12, // 20
5.12, 5.14, 5.16, 5.18, 5.20, 5.22, 5.22, 5.24, 5.26, 5.28, // 30
5.30, 5.32, 5.32, 5.34, 5.36, 5.38, 5.40, 5.42, 5.44, 5.46, // 40
5.48, 5.50, 5.50, 5.52, 5.54, 5.56, 5.58, 5.60, 5.62, 5.64, // 50
5.66, 5.68, 5.70, 5.72, 5.74, 5.76, 5.78, 5.80, 5.82, 5.86, // 60
5.88, 5.90, 5.92, 5.94, 5.96, 5.98, 6.00, 6.02, 6.04, 6.08, // 70
6.10, 6.12, 6.14, 6.16, 6.20, 6.22, 6.24, 6.28, 6.30, 6.32, // 80
6.34, 6.36, 6.40, 6.42, 6.44, 6.48, 6.50, 6.54, 6.56, 6.58, // 90
6.62, 6.64, 6.68, 6.70, 6.74, 6.76, 6.78, 6.82, 6.84, 6.88, // 100
6.92, 6.94, 6.98, 7.00, 7.04, 7.08, 7.12, 7.14, 7.18, 7.22, // 110
7.26, 7.28, 7.30, 7.34, 7.38, 7.42, 7.46, 7.50, 7.54, 7.58, // 120
7.62, 7.66, 7.70, 7.74, 7.78, 7.82, 7.86, 7.90, 7.92, 7.98, // 130
8.02, 8.06, 8.10, 8.16, 8.20, 8.26, 8.30, 8.34, 8.40, 8.44, // 140
8.50, 8.54, 8.60, 8.66, 8.68, 8.74, 8.78, 8.84, 8.90, 8.96, // 150
9.02, 9.08, 9.14, 9.20, 9.26, 9.32, 9.38, 9.44, 9.52, 9.58, // 160
9.62, 9.68, 9.76, 9.82, 9.90, 9.96, 10.04, 10.12, 10.18, 10.26, // 170
10.34, 10.42, 10.50, 10.58, 10.68, 10.76, 10.80, 10.88, 10.98, 11.08, // 180
11.16, 11.26, 11.36, 11.44, 11.54, 11.64, 11.74, 11.86, 11.96, 12.08, // 190
12.18, 12.30, 12.36, 12.48, 12.60, 12.72, 12.84, 12.96, 13.10, 13.24, // 200
13.36, 13.50, 13.64, 13.78, 13.94, 14.08, 14.24, 14.40, 14.48, 14.66, // 210
14.82, 15.00, 15.18, 15.36, 15.54, 15.74, 15.92, 16.12, 16.32, 16.54, // 220
16.76, 16.98, 17.22, 17.44, 17.58, 17.82, 18.08, 18.34, 18.62, 18.90, // 230
19.20, 19.48, 19.80, 20.10, 20.44, 20.78, 21.12, 21.50, 21.88, 22.26, // 240
22.48, 22.90, 23.34, 23.80, 24.26, 24.74, 25.26, 25.76, 26.32, 26.86, // 250
27.48, 28.12, 28.78, 29.50, 29.50, 29.50
}
};
const std::vector<double> umtrx_impl::_dcdc_val_to_volt(_dcdc_val_to_volt_init, &_dcdc_val_to_volt_init[256]);
/***********************************************************************
* Property tree "alias" function
@@ -207,7 +179,6 @@ static mtu_result_t determine_mtu(const std::string &addr, const mtu_result_t &u
**********************************************************************/
umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
{
_umtrx_vga2_def = device_addr.cast<int>("lmsvga2", UMTRX_VGA2_DEF);
_device_ip_addr = device_addr["addr"];
UHD_MSG(status) << "UmTRX driver version: " << UMTRX_VERSION << std::endl;
UHD_MSG(status) << "Opening a UmTRX device... " << _device_ip_addr << std::endl;
@@ -299,36 +270,6 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
_tree->create<std::string>(mb_path / "hwrev").set(get_hw_rev());
UHD_MSG(status) << "Detected UmTRX " << get_hw_rev() << std::endl;
_hw_dcdc_ver = device_addr.cast<int>("dcdc_ver", -1);
if (_hw_dcdc_ver < 0)
{
detect_hw_dcdc_ver(mb_path);
} else {
UHD_ASSERT_THROW(_hw_dcdc_ver < DCDC_VER_COUNT);
UHD_MSG(status) << "Using DCDC version " << _hw_dcdc_ver << std::endl;
}
_tree->create<int>(mb_path / "hwdcdc_ver").set(_hw_dcdc_ver);
////////////////////////////////////////////////////////////////////////
// setup umsel2 control when present
////////////////////////////////////////////////////////////////////////
const std::string detect_umsel = device_addr.get("umsel", "off");
if (detect_umsel != "off")
{
//TODO delect umsel2 automatically with I2C communication
const bool umsel_verbose = device_addr.has_key("umsel_verbose");
_umsel2 = umsel2_ctrl::make(_ctrl/*peek*/, _ctrl/*spi*/, this->get_master_clock_rate(), umsel_verbose);
}
//register lock detect for umsel2
if (_umsel2)
{
_tree->create<sensor_value_t>(mb_path / "dboards" / "A" / "rx_frontends" / "0" / "sensors" / "aux_lo_locked")
.publish(boost::bind(&umsel2_ctrl::get_locked, _umsel2, 1));
_tree->create<sensor_value_t>(mb_path / "dboards" / "B" / "rx_frontends" / "0" / "sensors" / "aux_lo_locked")
.publish(boost::bind(&umsel2_ctrl::get_locked, _umsel2, 2));
}
////////////////////////////////////////////////////////////////////////
// configure diversity switches
////////////////////////////////////////////////////////////////////////
@@ -549,8 +490,8 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
////////////////////////////////////////////////////////////////////
// create RF frontend interfacing
////////////////////////////////////////////////////////////////////
_lms_ctrl["A"] = lms6002d_ctrl::make(_ctrl/*spi*/, SPI_SS_LMS1, this->get_master_clock_rate() / _pll_div);
_lms_ctrl["B"] = lms6002d_ctrl::make(_ctrl/*spi*/, SPI_SS_LMS2, this->get_master_clock_rate() / _pll_div);
_lms_ctrl["A"] = lms6002d_ctrl::make(_ctrl/*spi*/, SPI_SS_LMS1, SPI_SS_AUX1, this->get_master_clock_rate() / _pll_div);
_lms_ctrl["B"] = lms6002d_ctrl::make(_ctrl/*spi*/, SPI_SS_LMS2, SPI_SS_AUX2, this->get_master_clock_rate() / _pll_div);
// LMS dboard do not have physical eeprom so we just hardcode values from host/lib/usrp/dboard/db_lms.cpp
dboard_eeprom_t rx_db_eeprom, tx_db_eeprom, gdb_db_eeprom;
@@ -613,8 +554,7 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
} else {
// Set LMS internal VGA1 gain to optimal value
// VGA2 will be set in the set_tx_power()
const int vga1 = device_addr.cast<int>("lmsvga1", UMTRX_VGA1_DEF);
ctrl->set_tx_gain(vga1, "VGA1");
ctrl->set_tx_gain(UMTRX_VGA1_DEF, "VGA1");
_tx_power_range[fe_name] = generate_tx_power_range(fe_name);
// Use PA control to control output power
@@ -630,9 +570,9 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
//rx freq
_tree->create<double>(rx_rf_fe_path / "freq" / "value")
.coerce(boost::bind(&umtrx_impl::set_rx_freq, this, fe_name, _1));
.coerce(boost::bind(&lms6002d_ctrl::set_rx_freq, ctrl, _1));
_tree->create<meta_range_t>(rx_rf_fe_path / "freq" / "range")
.publish(boost::bind(&umtrx_impl::get_rx_freq_range, this, fe_name));
.publish(boost::bind(&lms6002d_ctrl::get_rx_freq_range, ctrl));
_tree->create<bool>(rx_rf_fe_path / "use_lo_offset").set(false);
//tx freq
@@ -707,42 +647,15 @@ umtrx_impl::umtrx_impl(const device_addr_t &device_addr)
.subscribe(boost::bind(&umtrx_impl::set_dc_offset_correction, this, fe_name, _1))
.set(std::complex<double>(dc_i, dc_q));
//rx cal props
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rx_fe_dc_i" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxfe_dc_i, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxfe_dc_i, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rx_fe_dc_q" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxfe_dc_q, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxfe_dc_q, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rx_lpf_dc_i" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxlpf_dc_i, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxlpf_dc_i, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rx_lpf_dc_q" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxlpf_dc_q, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxlpf_dc_q, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rxvga2_dc_reference" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxvga2_dc_reference, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxvga2_dc_reference, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rxvga2a_dc_i" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxvga2a_dc_i, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxvga2a_dc_i, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rxvga2a_dc_q" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxvga2a_dc_q, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxvga2a_dc_q, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rxvga2b_dc_i" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxvga2b_dc_i, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxvga2b_dc_i, ctrl, _1));
_tree->create<uint8_t>(rx_rf_fe_path / "lms6002d" / "rxvga2b_dc_q" / "value")
.publish(boost::bind(&lms6002d_ctrl::get_rxvga2b_dc_q, ctrl))
.subscribe(boost::bind(&lms6002d_ctrl::set_rxvga2b_dc_q, ctrl, _1));
// Alias diversity switch control from mb_path
property_alias<bool>(_tree, mb_path / "divsw"+(fe_name=="A"?"1":"2"), rx_rf_fe_path / "diversity");
}
//TCXO DAC calibration control
//set TCXO DAC calibration value, which is read from mboard EEPROM
const std::string tcxo_dac = _iface->mb_eeprom.get("tcxo-dac", "");
if (not tcxo_dac.empty()) _tree->create<uint16_t>(mb_path / "tcxo_dac" / "value")
.subscribe(boost::bind(&umtrx_impl::set_tcxo_dac, this, _iface, _1));
.subscribe(boost::bind(&umtrx_impl::set_tcxo_dac, this, _iface, _1))
.set(boost::lexical_cast<uint16_t>(tcxo_dac));
////////////////////////////////////////////////////////////////////
// post config tasks
@@ -799,13 +712,12 @@ umtrx_impl::~umtrx_impl(void)
int umtrx_impl::volt_to_dcdc_r(double v)
{
if (v <= _dcdc_val_to_volt[_hw_dcdc_ver][0])
if (v <= _dcdc_val_to_volt[0])
return 0;
else if (v >= _dcdc_val_to_volt[_hw_dcdc_ver][255])
else if (v >= _dcdc_val_to_volt[255])
return 255;
else
return std::lower_bound(&_dcdc_val_to_volt[_hw_dcdc_ver][0], &_dcdc_val_to_volt[_hw_dcdc_ver][256], v) -
&_dcdc_val_to_volt[_hw_dcdc_ver][0];
return std::lower_bound(_dcdc_val_to_volt.begin(), _dcdc_val_to_volt.end(), v) - _dcdc_val_to_volt.begin();
}
void umtrx_impl::set_pa_dcdc_r(uint8_t val)
@@ -825,7 +737,7 @@ uhd::gain_range_t umtrx_impl::generate_tx_power_range(const std::string &which)
// maintain high signal quality.
uhd::gain_range_t pa_range = generate_pa_power_range(which);
// UHD_MSG(status) << "Original PA output power range: " << pa_range.to_pp_string() << std::endl;
uhd::gain_range_t vga_range(pa_range.start() - (_umtrx_vga2_def-UMTRX_VGA2_MIN), pa_range.start()-1, 1.0);
uhd::gain_range_t vga_range(pa_range.start() - (UMTRX_VGA2_DEF-UMTRX_VGA2_MIN), pa_range.start()-1, 1.0);
uhd::gain_range_t res_range(vga_range);
res_range.insert(res_range.end(), pa_range.begin(), pa_range.end());
// UHD_MSG(status) << "Generated Tx output power range: " << res_range.to_pp_string() << std::endl;
@@ -851,16 +763,16 @@ double umtrx_impl::set_tx_power(double power, const std::string &which)
if (power >= min_pa_power)
{
UHD_MSG(status) << "Setting Tx power using PA (VGA2=" << _umtrx_vga2_def << ", PA=" << power << ")" << std::endl;
UHD_MSG(status) << "Setting Tx power using PA (VGA2=" << UMTRX_VGA2_DEF << ", PA=" << power << ")" << std::endl;
// Set VGA2 to the recommended value and use PA to control Tx power
_lms_ctrl[which]->set_tx_gain(_umtrx_vga2_def, "VGA2");
_lms_ctrl[which]->set_tx_gain(UMTRX_VGA2_DEF, "VGA2");
actual_power = set_pa_power(power, which);
} else {
double vga2_gain = _umtrx_vga2_def - (min_pa_power-power);
double vga2_gain = UMTRX_VGA2_DEF - (min_pa_power-power);
UHD_MSG(status) << "Setting Tx power using VGA2 (VGA2=" << vga2_gain << ", PA=" << min_pa_power << ")" << std::endl;
// Set PA output power to minimum and use VGA2 to control Tx power
actual_power = _lms_ctrl[which]->set_tx_gain(vga2_gain, "VGA2");
actual_power = set_pa_power(min_pa_power, which) - (_umtrx_vga2_def-actual_power);
actual_power = set_pa_power(min_pa_power, which) - (UMTRX_VGA2_DEF-actual_power);
}
return actual_power;
@@ -959,49 +871,6 @@ uint8_t umtrx_impl::dc_offset_double2int(double corr)
return (int)(corr*128 + 128.5);
}
double umtrx_impl::set_rx_freq(const std::string &which, const double freq)
{
if (_umsel2)
{
const double target_lms_freq = (which=="A")?UMSEL2_CH1_LMS_IF:UMSEL2_CH2_LMS_IF;
const double actual_lms_freq = _lms_ctrl[which]->set_rx_freq(target_lms_freq);
const double target_umsel_freq = freq - actual_lms_freq;
const double actual_umsel_freq = _umsel2->set_rx_freq((which=="A")?1:2, target_umsel_freq);
/*
std::cout << "target_total_freq " << freq/1e6 << " MHz" << std::endl;
std::cout << "target_lms_freq " << target_lms_freq/1e6 << " MHz" << std::endl;
std::cout << "actual_lms_freq " << actual_lms_freq/1e6 << " MHz" << std::endl;
std::cout << "target_umsel_freq " << target_umsel_freq/1e6 << " MHz" << std::endl;
std::cout << "actual_umsel_freq " << actual_umsel_freq/1e6 << " MHz" << std::endl;
std::cout << "actual_total_freq " << (actual_umsel_freq + actual_lms_freq)/1e6 << " MHz" << std::endl;
//*/
return actual_umsel_freq + actual_lms_freq;
}
else
{
return _lms_ctrl[which]->set_rx_freq(freq);
}
}
uhd::freq_range_t umtrx_impl::get_rx_freq_range(const std::string &which) const
{
if (_umsel2)
{
const double target_lms_freq = (which=="A")?UMSEL2_CH1_LMS_IF:UMSEL2_CH2_LMS_IF;
const uhd::freq_range_t range_umsel = _umsel2->get_rx_freq_range((which=="A")?1:2);
return uhd::freq_range_t(
range_umsel.start()+target_lms_freq,
range_umsel.stop()+target_lms_freq);
}
else
{
return _lms_ctrl[which]->get_rx_freq_range();
}
}
uhd::sensor_value_t umtrx_impl::read_temp_c(const std::string &which)
{
boost::recursive_mutex::scoped_lock l(_i2c_mutex);
@@ -1132,7 +1001,7 @@ void umtrx_impl::detect_hw_rev(const fs_path& mb_path)
pa_low = pa_low_env;
}
if (pa_low.empty())
_pa_nlow = true; //Turn off Vin bypass by default
_pa_nlow = false;
else
_pa_nlow = (boost::lexical_cast<int>(pa_low) == 0);
@@ -1192,34 +1061,3 @@ const char* umtrx_impl::get_hw_rev() const
default: return "[unknown]";
}
}
void umtrx_impl::detect_hw_dcdc_ver(const uhd::fs_path &)
{
_hw_dcdc_ver = DCDC_VER_2_3_1_OLD;
if (_hw_rev < UMTRX_VER_2_3_1)
{
return;
}
uint8_t old = _pa_dcdc_r;
bool old_pa_nlow = _pa_nlow;
set_nlow(true);
set_pa_dcdc_r(0);
boost::this_thread::sleep(boost::posix_time::seconds(1));
double v_actual = read_dc_v("DCOUT").to_real();
double err_min = std::abs(v_actual - _dcdc_val_to_volt[0][0]);
for (unsigned j = 1; j < DCDC_VER_COUNT; ++j) {
double err = std::abs(v_actual - _dcdc_val_to_volt[j][0]);
if (err < err_min) {
err_min = err;
_hw_dcdc_ver = j;
}
}
set_pa_dcdc_r(old);
set_nlow(old_pa_nlow);
UHD_MSG(status) << "Detected UmTRX DCDC ver. " << _hw_dcdc_ver
<< " (err: " << err_min << ")" << std::endl;
}

25
host/umtrx_impl.hpp
View File

@@ -31,7 +31,6 @@
#include "ads1015_ctrl.hpp"
#include "tmp102_ctrl.hpp"
#include "power_amp.hpp"
#include "umsel2_ctrl.hpp"
#include <uhd/usrp/mboard_eeprom.hpp>
#include <uhd/property_tree.hpp>
#include <uhd/device.hpp>
@@ -119,17 +118,8 @@ private:
UMTRX_VER_2_3_1
};
enum umtrx_dcdc_ver {
DCDC_VER_2_3_1_OLD = 0,
DCDC_VER_2_3_1_NEW = 1,
DCDC_VER_COUNT //Should be the last
};
// hardware revision
umtrx_hw_rev _hw_rev;
int _hw_dcdc_ver;
unsigned _pll_div;
const char* get_hw_rev() const;
@@ -138,16 +128,16 @@ private:
static const int UMTRX_VGA2_DEF;
static const int UMTRX_VGA2_MIN;
static const double _dcdc_val_to_volt[umtrx_impl::DCDC_VER_COUNT][256];
// Conversion table for converting DCDC_R values to actual voltages.
static const std::vector<double> _dcdc_val_to_volt;
// Find a dcdc_r value to approximate requested Vout voltage
static int volt_to_dcdc_r(double v);
ads1015_ctrl _sense_pwr;
ads1015_ctrl _sense_dc;
tmp102_ctrl _temp_side_a;
tmp102_ctrl _temp_side_b;
// Optimal device specific value
int _umtrx_vga2_def;
//PA control
bool _pa_nlow;
bool _pa_en1;
@@ -162,7 +152,6 @@ private:
std::string _device_ip_addr;
umtrx_iface::sptr _iface;
umtrx_fifo_ctrl::sptr _ctrl;
umsel2_ctrl::sptr _umsel2;
//controls for perifs
uhd::dict<std::string, lms6002d_ctrl::sptr> _lms_ctrl;
@@ -192,7 +181,6 @@ private:
void set_tx_fe_corrections(const std::string &mb, const std::string &board, const double);
void set_tcxo_dac(const umtrx_iface::sptr &, const uint16_t val);
void detect_hw_rev(const uhd::fs_path &mb_path);
void detect_hw_dcdc_ver(const uhd::fs_path &mb_path);
void commit_pa_state();
void set_enpa1(bool en);
void set_enpa2(bool en);
@@ -207,11 +195,6 @@ private:
uhd::transport::zero_copy_if::sptr make_xport(const size_t which, const uhd::device_addr_t &args);
std::complex<double> get_dc_offset_correction(const std::string &which) const;
void set_dc_offset_correction(const std::string &which, const std::complex<double> &corr);
double set_rx_freq(const std::string &which, const double freq);
uhd::freq_range_t get_rx_freq_range(const std::string &which) const;
// Find a dcdc_r value to approximate requested Vout voltage
int volt_to_dcdc_r(double v);
static double dc_offset_int2double(uint8_t corr);
static uint8_t dc_offset_double2int(double corr);

33
host/umtrx_monitor.cpp
View File

@@ -49,20 +49,15 @@ namespace asio = boost::asio;
* print json.loads(f.readline())
* {u'result': u'true'}
*
* #get the value of a tree entry, types can be BOOL, INT, DOUBLE, COMPLEX, SENSOR, RANGE
* #get the value of a tree entry, types can be BOOL, INT, DOUBLE, SENSOR, RANGE
* s.send(json.dumps(dict(action='GET', path='/mboards/0/sensors/tempA', type='SENSOR'))+'\n')
* print json.loads(f.readline())
* {u'result': {u'unit': u'C', u'name': u'TempA', u'value': u'61.625000'}}
*
* #set the value of a tree entry, types can be BOOL, INT, DOUBLE, COMPLEX
* #set the value of a tree entry, types can be BOOL, INT, DOUBLE
* s.send(json.dumps(dict(action='SET', path='/mboards/0/dboards/A/rx_frontends/0/freq/value', type='DOUBLE', value=1e9))+'\n')
* print json.loads(f.readline())
* {} #empty response means no error
*
* #in case of COMPLEX 'value' is an array of [real, imag] values
* s.send(json.dumps(dict(action='SET', path='/mboards/0/rx_frontends/A/dc_offset/value', type='COMPLEX', value=[0.1, 0.0]))+'\n')
* print json.loads(f.readline())
* {} #empty response means no error
*/
void umtrx_impl::status_monitor_start(const uhd::device_addr_t &device_addr)
@@ -192,22 +187,10 @@ void umtrx_impl::client_query_handle1(const boost::property_tree::ptree &request
else if (action == "GET")
{
const std::string type = request.get("type", "");
if (type.empty()) response.put("error", "type field not specified: STRING, BOOL, INT, DOUBLE, COMPLEX, SENSOR, RANGE");
else if (type == "STRING") response.put("result", _tree->access<std::string>(path).get());
if (type.empty()) response.put("error", "type field not specified: BOOL, INT, DOUBLE, SENSOR, RANGE");
else if (type == "BOOL") response.put("result", _tree->access<bool>(path).get());
else if (type == "INT") response.put("result", _tree->access<int>(path).get());
else if (type == "DOUBLE") response.put("result", _tree->access<double>(path).get());
else if (type == "COMPLEX")
{
boost::property_tree::ptree result;
boost::property_tree::ptree ptree_i, ptree_q;
const std::complex<double> c = _tree->access<std::complex<double> >(path).get();
ptree_i.put("", c.real());
ptree_q.put("", c.imag());
result.push_back(std::make_pair("", ptree_i));
result.push_back(std::make_pair("", ptree_q));
response.add_child("result", result);
}
else if (type == "SENSOR")
{
boost::property_tree::ptree result;
@@ -235,18 +218,10 @@ void umtrx_impl::client_query_handle1(const boost::property_tree::ptree &request
else if (action == "SET")
{
const std::string type = request.get("type", "");
if (type.empty()) response.put("error", "type field not specified: STRING, BOOL, INT, DOUBLE, COMPLEX");
else if (type == "STRING") _tree->access<std::string>(path).set(request.get<std::string>("value"));
if (type.empty()) response.put("error", "type field not specified: BOOL, INT, DOUBLE");
else if (type == "BOOL") _tree->access<bool>(path).set(request.get<bool>("value"));
else if (type == "INT") _tree->access<int>(path).set(request.get<int>("value"));
else if (type == "DOUBLE") _tree->access<double>(path).set(request.get<double>("value"));
else if (type == "COMPLEX")
{
boost::property_tree::ptree value = request.get_child("value");
double i = value.front().second.get<double>("");
double q = value.back().second.get<double>("");
_tree->access<std::complex<double> >(path).set(std::complex<double>(i, q));
}
else response.put("error", "unknown type: " + type);
}
else if (action == "HAS")

3
host/umtrx_regs.hpp
View File

@@ -104,9 +104,6 @@ localparam SR_SPI_CORE = 185; // 3
#define U2_REG_TIME64_HI_RB_PPS READBACK_BASE + 4*14
#define U2_REG_TIME64_LO_RB_PPS READBACK_BASE + 4*15
#define AUX_LD1_IRQ_BIT (1 << 14)
#define AUX_LD2_IRQ_BIT (1 << 15)
/////////////////////////////////////////////////
// LMS regs
////////////////////////////////////////////////

10
host/usrp2/fw_common.h
View File

@@ -32,7 +32,7 @@ extern "C" {
//fpga and firmware compatibility numbers
#define USRP2_FPGA_COMPAT_NUM 9
#define USRP2_FW_COMPAT_NUM 12
#define USRP2_FW_VER_MINOR 3
#define USRP2_FW_VER_MINOR 2
//used to differentiate control packets over data port
#define USRP2_INVALID_VRT_HEADER 0
@@ -127,12 +127,8 @@ typedef enum{
typedef enum{
UMTRX_ZPU_REQUEST_GET_VCTCXO_DAC = 1,
UMTRX_ZPU_REQUEST_SET_VCTCXO_DAC = 2,
UMTRX_ZPU_REQUEST_SET_GPSDO_DEBUG = 3,
UMTRX_ZPU_REQUEST_GET_GPSDO_FREQ = 4,
UMTRX_ZPU_REQUEST_GET_GPSDO_FREQ_LPF = 5,
UMTRX_ZPU_REQUEST_GET_GPSDO_PPS_SECS = 6,
UMTRX_ZPU_REQUEST_SET_GPSDO_PPS_TICKS = 7
UMTRX_ZPU_REQUEST_SET_VCTCXO_DAC = 2
/* GPSDO control to be here */
} umtrx_zpu_action_t;
typedef struct{

2
host/utils/CMakeLists.txt
View File

@@ -2,10 +2,10 @@
# Build and Install the UmTRX utils
########################################################################
INSTALL(PROGRAMS
umtrx_net_burner
umtrx_nmea
umtrx_gps_coord
umtrx_auto_calibration
umtrx_firmware
DESTINATION bin
)

6
host/utils/collectd/umtrx.conf
View File

@@ -1,6 +0,0 @@
TypesDB "/usr/share/collectd/umtrx.types.db"
LoadPlugin exec
<Plugin exec>
Exec "fairwaves-monitoring" "/usr/share/umtrx/umtrx2collectd.py"
</Plugin>

1
host/utils/collectd/umtrx.types.db
View File

@@ -1 +0,0 @@
sensor value:GAUGE:U:U

54
host/utils/collectd/umtrx2collectd.py
View File

@@ -1,54 +0,0 @@
#!/usr/bin/python -u
# -*- coding: utf-8 -*-
import os
import sched, time
from umtrx_property_tree import umtrx_property_tree
from umtrx_vswr import umtrx_vswr
BOARD_ID = "0"
SENSORS_PATH = "/mboards/{id}/sensors".format(id=BOARD_ID)
VSWR_CALIBRATION = 0 # = TM10_VSWR_cal
HOSTNAME = os.environ['COLLECTD_HOSTNAME'] if 'COLLECTD_HOSTNAME' in os.environ else 'localhost'
INTERVAL = os.environ['COLLECTD_INTERVAL'] if 'COLLECTD_INTERVAL' in os.environ else '60'
umtrx = umtrx_property_tree()
umtrx.connect()
# typically this yields: ['tempA', 'tempB', 'voltagePR1', 'voltagePF1', 'voltagePR2', 'voltagePF2', 'voltagezero', 'voltageVin', 'voltageVinPA', 'voltageDCOUT']
sensors_list = umtrx.list_path_raw(SENSORS_PATH).get("result", [])
def publish():
now = time.time()
current_sensors = {sensor: umtrx.query_sensor_value(SENSORS_PATH + "/" + sensor) for sensor in sensors_list}
for channel in ["1", "2"]:
vpf_name = "voltagePF" + channel
vpr_name = "voltagePR" + channel
if vpf_name in current_sensors and vpr_name in current_sensors:
vswr = umtrx_vswr(float(current_sensors[vpf_name]), float(current_sensors[vpr_name]), VSWR_CALIBRATION)
current_sensors["VSWR" + channel] = vswr.vswr()
current_sensors["ReturnLoss" + channel] = vswr.return_loss()
for name, value in current_sensors.items():
print "PUTVAL {host}/umtrx-{id}/sensor-{name} interval={interval} {now}:{value}".format(
host=HOSTNAME, id=BOARD_ID, name=name.lower(), interval=INTERVAL, now=now, value=value)
s = sched.scheduler(time.time, time.sleep)
def timer_loop():
s.enter(float(INTERVAL), 1, timer_loop, ())
publish()
timer_loop()
s.run()
umtrx.close()

16
host/utils/umtrx_firmware
View File

@@ -1,16 +0,0 @@
#!/bin/bash
case $1 in
flash )
umtrx_net_burner --addr=192.168.10.2 --fpga=/usr/share/umtrx/firmware/u2plus_umtrx_v2.bin --fw=/usr/share/umtrx/firmware/umtrx_txrx_uhd.bin --reset
;;
check )
;;
* )
cat <<-EOF
Usage:
$0 flash - burn packaged firmware to umtrx
$0 check - compare versions of packaged firmware and one installed on umtrx
EOF
;;
esac

0
host/utils/umtrx_net_burner.py → host/utils/umtrx_net_burner
View File

55
host/utils/umtrx_property_tree.py
View File

@@ -26,7 +26,7 @@ class umtrx_property_tree:
d = dict(action=action, path=path)
if value_type is not None: d['type'] = value_type
if value is not None: d['value'] = value
return self.s.send(bytes(json.dumps(d)+'\n', 'UTF-8'))
return self.s.send(json.dumps(d)+'\n')
def _recv_response(self):
resp = self.f.readline().strip()
@@ -51,55 +51,37 @@ class umtrx_property_tree:
self._send_request('GET', path, value_type='DOUBLE')
return self._recv_response()
def query_sensor_raw(self, path):
self._send_request('GET', path, value_type='SENSOR')
def query_sensor_raw(self, sensor_path):
self._send_request('GET', sensor_path, value_type='SENSOR')
return self._recv_response()
def query_range_raw(self, path):
self._send_request('GET', path, value_type='RANGE')
return self._recv_response()
def query_string_raw(self, path):
self._send_request('GET', path, value_type='STRING')
return self._recv_response()
def query_complex_raw(self, path):
self._send_request('GET', path, value_type='COMPLEX')
return self._recv_response()
#
# Getters (value)
#
def query_bool_value(self, path):
res = self.query_bool_raw(path)
return res['result']
res = self.query_bool_raw(sensor_path)
return res['result']['value']
def query_int_value(self, path):
res = self.query_int_raw(path)
return int(res['result'])
res = self.query_int_raw(sensor_path)
return res['result']['value']
def query_double_value(self, path):
res = self.query_double_raw(path)
return float(res['result'])
res = self.query_double_raw(sensor_path)
return res['result']['value']
def query_sensor_value(self, path):
res = self.query_sensor_raw(path)
def query_sensor_value(self, sensor_path):
res = self.query_sensor_raw(sensor_path)
return res['result']['value']
def query_range_value(self, path):
res = self.query_range_raw(path)
return res['result']
def query_string_value(self, path):
res = self.query_string_raw(path)
return res['result']
def query_complex_value(self, path):
res = self.query_complex_raw(path)
i = float(res['result'][0])
q = float(res['result'][1])
return complex(i, q)
res = self.query_range_raw(sensor_path)
return res['result']['value']
#
# Setters
@@ -117,17 +99,6 @@ class umtrx_property_tree:
self._send_request('SET', path, value_type='DOUBLE', value=val)
return self._recv_response()
def set_string(self, path, val):
self._send_request('SET', path, value_type='STRING', value=val)
return self._recv_response()
def set_complex(self, path, val):
if type(val) is complex:
# Convert complex to an array
val = [val.real, val.imag]
self._send_request('SET', path, value_type='COMPLEX', value=val)
return self._recv_response()
#
# Check path presence and list paths
#

20
host/utils/umtrx_query_versions.py
View File

@@ -1,20 +0,0 @@
#!/usr/bin/env python
# -*- coding: utf-8 -*-
##########################
### Query sensors
##########################
from umtrx_property_tree import umtrx_property_tree
s = umtrx_property_tree()
s.connect()
mb_path="/mboards/0"
fpga_version = s.query_string_value(mb_path+"/fpga_version")
fw_version = s.query_string_value(mb_path+"/fw_version")
print "FPGA bitstream version: %s" % fpga_version
print "ZPU firmware version: %s" % fw_version
s.close()

8
host/utils/umtrx_vswr.py
View File

@@ -46,8 +46,6 @@ class umtrx_vswr:
gamma = self._gamma
if gamma == 1.0:
return float("inf")
elif gamma > 1.0:
return float("nan")
else:
return (1+gamma)/(1-gamma)
@@ -56,21 +54,15 @@ class umtrx_vswr:
gamma = self._gamma
if gamma == 1.0:
return float("-inf")
elif gamma > 1.0:
return float("nan")
else:
return -10.0 * math.log(1.0-gamma*gamma, 10)
def pf_rate(self):
''' Estimated reflected power rate, % '''
gamma = self._gamma
if gamma > 1.0:
return float("nan")
return 1.0 - gamma*gamma
def pr_rate(self):
''' Estimated reflected power rate, % '''
gamma = self._gamma
if gamma > 1.0:
return float("nan")
return gamma*gamma

BIN
images/u2plus_umtrx_v2.bin
View File

Binary file not shown.

BIN
images/u2plus_umtrx_v2_4ddc.bin
View File

Binary file not shown.

BIN
images/umtrx_txrx_uhd.bin Normal file → Executable file
View File

Binary file not shown.

15
zpu/CMakeLists.txt
View File

@@ -87,8 +87,6 @@ INCLUDE_DIRECTORIES(
FIND_PROGRAM(LINKER zpu-elf-ld)
FIND_PROGRAM(OBJCOPY zpu-elf-objcopy)
FIND_PROGRAM(OBJDUMP zpu-elf-objdump)
FIND_PROGRAM(ELFSIZE zpu-elf-size)
FIND_PROGRAM(HEXDUMP hexdump)
########################################################################
@@ -130,19 +128,6 @@ MACRO(GEN_OUTPUTS target)
)
ENDMACRO(GEN_OUTPUTS)
MACRO(TEST_STACK_SIZE target minsize)
GET_FILENAME_COMPONENT(name ${target} NAME_WE)
ADD_CUSTOM_COMMAND(
OUTPUT ${name}.freestack DEPENDS ${target}
COMMAND echo $$\(\(16383 - $$\(${ELFSIZE} ${target} | tail -n1 | { read text data bss dec hex\; echo $$dec\; }\)\)\) > ${name}.freestack
COMMAND echo Free stack space for ${target} is `cat ${name}.freestack`
COMMAND if [ `cat ${name}.freestack` -le ${minsize} ]\; then echo ERROR Image stack overflow `cat ${name}.freestack` is less than ${minsize}\; exit 1\; fi
)
#add a top level target for output files
ADD_CUSTOM_TARGET(
${name}_freestack ALL DEPENDS ${name}.freestack
)
ENDMACRO(TEST_STACK_SIZE)
########################################################################
# Add the subdirectories
########################################################################

33
zpu/apps/txrx_uhd.c
View File

@@ -111,8 +111,8 @@ static void handle_udp_ctrl_packet(
//ensure that the protocol versions match
if (payload_len >= sizeof(uint32_t) && ctrl_data_in->proto_ver != USRP2_FW_COMPAT_NUM){
if (ctrl_data_in->proto_ver) printf("Received a control packet with compatibility number %d. Replying with our compatibility number %d.\n",
ctrl_data_in->proto_ver, USRP2_FW_COMPAT_NUM
if (ctrl_data_in->proto_ver) printf("!Error in control packet handler: Expected compatibility number %d, but got %d\n",
USRP2_FW_COMPAT_NUM, ctrl_data_in->proto_ver
);
#ifdef UMTRX
ctrl_data_in_id = UMTRX_CTRL_ID_REQUEST;
@@ -123,7 +123,7 @@ static void handle_udp_ctrl_packet(
//ensure that this is not a short packet
if (payload_len < sizeof(usrp2_ctrl_data_t)){
printf("Received a short packet: Expected payload length %d, but got %d. Sending USRP2_CTRL_ID_HUH_WHAT\n",
printf("!Error in control packet handler: Expected payload length %d, but got %d\n",
(int)sizeof(usrp2_ctrl_data_t), payload_len
);
ctrl_data_in_id = USRP2_CTRL_ID_HUH_WHAT;
@@ -162,25 +162,10 @@ static void handle_udp_ctrl_packet(
ctrl_data_out.data.zpu_action.action = ctrl_data_in->data.zpu_action.action;
switch (ctrl_data_in->data.zpu_action.action) {
case UMTRX_ZPU_REQUEST_GET_VCTCXO_DAC:
ctrl_data_out.data.zpu_action.data = (uint32_t)gpsdo_get_dac();
ctrl_data_out.data.zpu_action.data = (uint32_t)get_vctcxo_dac();
break;
case UMTRX_ZPU_REQUEST_SET_VCTCXO_DAC:
gpsdo_set_dac((uint16_t)ctrl_data_in->data.zpu_action.data);
break;
case UMTRX_ZPU_REQUEST_SET_GPSDO_DEBUG:
gpsdo_set_debug((bool)ctrl_data_in->data.zpu_action.data);
break;
case UMTRX_ZPU_REQUEST_GET_GPSDO_FREQ:
ctrl_data_out.data.zpu_action.data = gpsdo_get_last_freq();
break;
case UMTRX_ZPU_REQUEST_GET_GPSDO_FREQ_LPF:
ctrl_data_out.data.zpu_action.data = gpsdo_get_lpf_freq();
break;
case UMTRX_ZPU_REQUEST_GET_GPSDO_PPS_SECS:
ctrl_data_out.data.zpu_action.data = gpsdo_get_last_pps_secs();
break;
case UMTRX_ZPU_REQUEST_SET_GPSDO_PPS_TICKS:
ctrl_data_out.data.zpu_action.data = gpsdo_get_last_pps_ticks();
set_vctcxo_dac((uint16_t)ctrl_data_in->data.zpu_action.data);
break;
}
}
@@ -329,12 +314,12 @@ main(void)
{
u2_init();
#ifdef BOOTLOADER
putstr("\nUmTRX bootloader\n");
putstr("\nUSRP N210 UDP bootloader\n");
#else
putstr("\nUmTRX production\n");
putstr("\nTxRx-UHD-ZPU\n");
#endif
printf("FPGA compatibility number: %d\n", USRP2_FPGA_COMPAT_NUM);
printf("Firmware: %d.%d-%x\n", USRP2_FW_COMPAT_NUM, USRP2_FW_VER_MINOR, GITHASH);
printf("Firmware compatibility number: %d\n", USRP2_FW_COMPAT_NUM);
//init readback for firmware minor version number
fw_regs[U2_FW_REG_VER_MINOR] = USRP2_FW_VER_MINOR;
@@ -382,8 +367,6 @@ main(void)
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
printf("Init is done\n");
while(true){
size_t num_lines;

1
zpu/lib/CMakeLists.txt
View File

@@ -47,5 +47,4 @@ SET(COMMON_SRCS
${CMAKE_SOURCE_DIR}/lib/banal.c
${CMAKE_SOURCE_DIR}/lib/udp_uart.c
${CMAKE_SOURCE_DIR}/lib/gpsdo.c
${CMAKE_SOURCE_DIR}/lib/time64.c
)

18
zpu/lib/eeprom.c
View File

@@ -1,6 +1,5 @@
/*
* Copyright 2007 Free Software Foundation, Inc.
* Copyright 2017 Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,8 +22,6 @@
static const int EEPROM_PAGESIZE = 16;
#define EEPROM_TCXO_DAC_OFFSET (0xFF-3)
bool find_safe_booted_flag(void) {
#ifdef NO_EEPROM
return 0;
@@ -94,18 +91,3 @@ eeprom_read (int i2c_addr, int eeprom_offset, void *buf, int len)
return true;
}
#endif
uint16_t
eeprom_read_tcxo_dac()
{
uint16_t val;
eeprom_read(USRP2_I2C_ADDR_MBOARD, EEPROM_TCXO_DAC_OFFSET, &val, 2);
return (val>>8)+(val<<8);
}
bool
eeprom_write_tcxo_dac(uint16_t tcxo_dac)
{
uint16_t val = (tcxo_dac>>8)+(tcxo_dac<<8);
return eeprom_write(USRP2_I2C_ADDR_MBOARD, EEPROM_TCXO_DAC_OFFSET, &val, 2);
}

39
zpu/lib/eeprom.h
View File

@@ -1,39 +0,0 @@
/*
* Copyright 2017 Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef INCLUDED_EEPROM_H
#define INCLUDED_EEPROM_H
/* Safe booted or not? (read from EEPROM) */
bool find_safe_booted_flag(void);
/* Store safe booted flag to EEPROM */
void set_safe_booted_flag(bool flag);
/* Write to EEPROM */
bool eeprom_write(int i2c_addr, int eeprom_offset, const void *buf, int len);
/* Read from EEPROM */
bool eeprom_read(int i2c_addr, int eeprom_offset, void *buf, int len);
/* Read TCXO DAC calibrtion value from EEPROM */
uint16_t eeprom_read_tcxo_dac();
/* Write TCXO DAC calibrtion value to EEPROM */
bool eeprom_write_tcxo_dac(uint16_t tcxo_dac);
#endif /* INCLUDED_EEPROM_H */

193
zpu/lib/gpsdo.c
View File

@@ -19,8 +19,6 @@
#include "u2_init.h"
#include "pic.h"
#include "spi.h"
#include "time64.h"
#include "eeprom.h"
#include "memory_map.h"
@@ -33,7 +31,7 @@
#include <string.h>
#include <stdbool.h>
static int gpsdo_debug = 0;
/* #define GPSDO_DEBUG 1 */
/* DAC */
@@ -41,13 +39,13 @@ static int gpsdo_debug = 0;
#define DAC_BITS 12
static uint16_t dac_value; /* Current DAC value */
uint16_t dac_value; /* Current DAC value */
static int
_set_vctcxo_dac(uint16_t v)
int
set_vctcxo_dac(uint16_t v)
{
#ifndef BOOTLOADER
if (gpsdo_debug) printf("DAC: %d\n", v);
#ifdef GPSDO_DEBUG
printf("DAC: %d\n", v);
#endif
dac_value = v;
return spi_transact(
@@ -57,8 +55,8 @@ _set_vctcxo_dac(uint16_t v)
);
}
static uint16_t
_get_vctcxo_dac(void)
uint16_t
get_vctcxo_dac(void)
{
return dac_value;
}
@@ -75,16 +73,11 @@ _get_vctcxo_dac(void)
#define MAX_INT ((1<<31)-1)
#define G_PID_PK 64
#define G_PID_IK 16
#define G_PID_DK 256
typedef struct {
/* Loop constants */
// int16_t Pk;
// int16_t Ik;
// int16_t Dk;
int16_t Pk;
int16_t Ik;
int16_t Dk;
int32_t max_error;
int32_t max_sum_error;
@@ -93,7 +86,6 @@ typedef struct {
int32_t val_prev;
/* State */
int32_t init_val;
int32_t err_sum;
} pid_data_t;
@@ -101,25 +93,18 @@ typedef struct {
static pid_data_t g_pid;
static void
_gpsdo_pid_init(int32_t init_val)
_gpsdo_pid_init(void)
{
/* Configure loop */
//g_pid.Pk = 64;
//g_pid.Ik = 16;
//g_pid.Dk = 256; /* Seems high but we LPF PID input so d is dampened */
g_pid.Pk = 64;
g_pid.Ik = 16;
g_pid.Dk = 256; /* Seems high but we LPF PID input so d is dampened */
/* Reset state */
g_pid.val_prev = PID_TARGET;
g_pid.init_val = init_val;
g_pid.err_sum = 0;
}
static void
_gpsdo_pid_first_step(int32_t val)
{
g_pid.val_prev = val;
}
static void
_gpsdo_pid_step(int32_t val)
{
@@ -136,14 +121,14 @@ _gpsdo_pid_step(int32_t val)
error = -PID_MAX_ERR;
/* Compute P term */
p_term = error * G_PID_PK;
p_term = error * g_pid.Pk;
/* Compute I term */
g_pid.err_sum += error;
i_term = g_pid.err_sum * G_PID_IK;
i_term = g_pid.err_sum * g_pid.Ik;
/* Compute D term */
d_term = (g_pid.val_prev - val) * G_PID_DK;
d_term = (g_pid.val_prev - val) * g_pid.Dk;
g_pid.val_prev = val;
/* Final value */
@@ -154,12 +139,8 @@ _gpsdo_pid_step(int32_t val)
else if (tot < -PID_MAX_DEV)
tot = -PID_MAX_DEV;
#ifndef BOOTLOADER
if (gpsdo_debug) printf("GPSDO: DAC = %d %d (P=%d, I=%d, D=%d)>>%d limit +-%d\n",
g_pid.init_val, tot, p_term, i_term, d_term, PID_SCALE_SHIFT, PID_MAX_DEV);
#endif
/* Update DAC */
_set_vctcxo_dac( g_pid.init_val + tot );
set_vctcxo_dac( PID_MID_VAL + tot );
}
@@ -167,23 +148,7 @@ _gpsdo_pid_step(int32_t val)
/* Driver */
/* ------ */
/* Extra bits of precision for g_val_lpf */
#define VAL_LPF_PRECISION 3
#define VAL_LPF_INIT_VALUE (PID_TARGET<<VAL_LPF_PRECISION)
#define SKIP_ON_FIRST_RUN_VAL 2
/* Value > 0 indicates first run. Value itself is a ocunter how many IRQs
* to skip before starting PID regulation. Value of 2 is selected, because
* (1) the first tick will produce incorrect frequency counter because frequency
* correction occue in the middle of counting and (2) we need one valid reading
* to initialize g_pid.val_prev used for calculation of the D component. Previously
* we always initialized g_pid.val_prev to a value of the ideal target value
* which resulted in excessive oscillations. */
static int8_t g_skip_on_first_run = SKIP_ON_FIRST_RUN_VAL;
static uint32_t g_val_lpf = VAL_LPF_INIT_VALUE;
static uint32_t g_prev_secs = 0;
static uint32_t g_prev_ticks = 0;
static uint32_t g_last_calc_freq = 0; /* Last calculated VCTCXO frequency */
static int32_t g_val_lpf = PID_TARGET;
static void
_gpsdo_irq_handler(unsigned irq)
@@ -191,125 +156,43 @@ _gpsdo_irq_handler(unsigned irq)
if (gpsdo_regs->csr & GPSDO_CSR_RDY)
{
/* Counter value */
uint32_t val = gpsdo_regs->cnt;
/* Read the current wall time */
uint32_t cur_secs, cur_ticks;
time64_read(&cur_secs, &cur_ticks);
int32_t val = gpsdo_regs->cnt;
#ifdef GPSDO_DEBUG
printf("GPSDO Count: %d\n", val);
#endif
/* Next request */
gpsdo_regs->csr = GPSDO_CSR_REQ;
#ifndef BOOTLOADER
if (gpsdo_debug) printf("GPSDO: Counter = %u @ %u sec %u ticks\n", val, cur_secs, cur_ticks);
#endif
/* TODO:: Save the current wall time to be able check
time passed since the last lock later. This is useful
e.g. to check whether we still have a GPS lock.*/
/* Check validity of value */
if (abs(val - PID_TARGET) < 100000)
{
/* Save calculated frequency */
g_last_calc_freq = val;
if (g_skip_on_first_run > 0) {
g_skip_on_first_run--;
g_val_lpf = val<<VAL_LPF_PRECISION;
#ifndef BOOTLOADER
printf("GPSDO init: Filtered counter = %u + %u/8\n",
(g_val_lpf>>VAL_LPF_PRECISION), (g_val_lpf&((1<<VAL_LPF_PRECISION)-1)));
#endif
_gpsdo_pid_first_step(val);
} else {
/* LPF the value */
/* Integer overlow warning! */
/* This works for val ~= 52M, but don't try to use it with much larger values - it will overflow */
g_val_lpf = (g_val_lpf * 7 + (val<<VAL_LPF_PRECISION) + 4) >> 3;
#ifndef BOOTLOADER
if (gpsdo_debug) printf("GPSDO: Filtered counter = %u + %u/8\n",
(g_val_lpf>>VAL_LPF_PRECISION), (g_val_lpf&((1<<VAL_LPF_PRECISION)-1)));
#endif
/* Update PID */
_gpsdo_pid_step(g_val_lpf>>VAL_LPF_PRECISION);
}
}
/* LPF the value */
g_val_lpf = (g_val_lpf * 7 + val + 4) >> 3;
/* Save the current wall time */
g_prev_secs = cur_secs;
g_prev_ticks = cur_ticks;
/* Update PID */
_gpsdo_pid_step(g_val_lpf);
}
}
}
void
gpsdo_init(void)
{
uint16_t tcxo_dac = eeprom_read_tcxo_dac();
printf("TCXO DAC: %d ", tcxo_dac);
if (tcxo_dac == 0xFFFF) {
tcxo_dac = PID_MID_VAL;
#ifndef BOOTLOADER
printf("(hardcoded init)\n");
#endif
} else {
#ifndef BOOTLOADER
printf("(init from EEPROM)\n");
#endif
}
/* Reset GPSDO */
g_skip_on_first_run = SKIP_ON_FIRST_RUN_VAL;
/* Set last saved freq to an invalid value */
g_last_calc_freq = 0;
/* Set the DAC to initial value */
_set_vctcxo_dac( tcxo_dac );
/* Set the DAC to mid value */
set_vctcxo_dac( PID_MID_VAL );
/* Register IRQ handler */
pic_register_handler(IRQ_GPSDO, _gpsdo_irq_handler);
/* Init PID */
_gpsdo_pid_init(tcxo_dac);
_gpsdo_pid_init();
/* Start request */
gpsdo_regs->csr = GPSDO_CSR_REQ;
/* Save the current wall time.
* We can use it to estimate time to lock */
time64_read(&g_prev_secs, &g_prev_ticks);
}
void gpsdo_set_debug(int level)
{
gpsdo_debug = level;
}
void gpsdo_set_dac(uint16_t v)
{
/* Reset PID */
_gpsdo_pid_init(v);
/* Reset GPSDO */
g_skip_on_first_run = SKIP_ON_FIRST_RUN_VAL;
/* Set the DAC value */
_set_vctcxo_dac(v);
}
uint16_t gpsdo_get_dac(void)
{
return _get_vctcxo_dac();
}
uint32_t gpsdo_get_last_freq(void)
{
return g_last_calc_freq;
}
uint32_t gpsdo_get_lpf_freq(void)
{
return g_val_lpf;
}
uint32_t gpsdo_get_last_pps_secs(void)
{
return g_prev_secs;
}
uint32_t gpsdo_get_last_pps_ticks(void)
{
return g_prev_ticks;
}

20
zpu/lib/gpsdo.h
View File

@@ -1,6 +1,5 @@
/*
* Copyright 2012 Sylvain Munaut <tnt@246tNt.com>
* Copyright 2017 Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,25 +21,10 @@
void gpsdo_init(void);
/* Enable/disable GPSDO debug printing */
void gpsdo_set_debug(int level);
/* Set value of the VCTCXO DAC */
void gpsdo_set_dac(uint16_t v);
int set_vctcxo_dac(uint16_t v);
/* Get the current VCTCXO DAC value */
uint16_t gpsdo_get_dac(void);
/* Get the last calculated VCTCXO frequency */
uint32_t gpsdo_get_last_freq(void);
/* Get the last alpha/8 filtered VCTCXO frequency (29.3 fixed point) */
uint32_t gpsdo_get_lpf_freq(void);
/* Get time (seconds part) of the last PPS pulse */
uint32_t gpsdo_get_last_pps_secs(void);
/* Get time (ticks part) of the last PPS pulse */
uint32_t gpsdo_get_last_pps_ticks(void);
uint16_t get_vctcxo_dac(void);
#endif /* INCLUDED_GPSDO_H */

20
zpu/lib/i2c.c
View File

@@ -38,13 +38,6 @@ static uint16_t prescaler_values[MAX_WB_DIV+1] = {
#define WATCHDOG 50000
#ifndef BOOTLOADER
static void _print_wderr(const char* f)
{
printf("i2c_%s WATCHDOG failed!", f);
}
#endif
void
i2c_init(void)
{
@@ -70,11 +63,10 @@ wait_for_xfer(void)
unsigned i = WATCHDOG;
while ((i != 0) && (i2c_regs->cmd_status & I2C_ST_TIP)) // wait for xfer to complete
--i;
#ifndef BOOTLOADER
if (i == 0) {
_print_wderr("xfer");
puts("wait_for_xfer WATCHDOG failed!");
}
#endif
}
static inline bool
@@ -98,9 +90,7 @@ i2c_read (unsigned char i2c_addr, unsigned char *buf, unsigned int len)
while ((i != 0) && (i2c_regs->cmd_status & I2C_ST_BUSY))
--i;
if (i == 0) {
#ifndef BOOTLOADER
_print_wderr("read");
#endif
puts("i2c_read WATCHDOG failed!");
return false;
}
@@ -130,9 +120,7 @@ i2c_write(unsigned char i2c_addr, const unsigned char *buf, unsigned int len)
while ((i != 0) && (i2c_regs->cmd_status & I2C_ST_BUSY))
--i;
if (i == 0) {
#ifndef BOOTLOADER
_print_wderr("write");
#endif
puts("i2c_write WATCHDOG failed!");
return false;
}

93
zpu/lib/time64.c
View File

@@ -1,93 +0,0 @@
/*
* Copyright 2017 Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "memory_map.h"
/* printf headers */
//#include "nonstdio.h"
/* standard headers */
#include <stddef.h>
//#include <stdlib.h>
//#include <string.h>
#include <stdbool.h>
#include <limits.h>
#define UINT32_MAX UINT_MAX
void
time64_read(uint32_t *secs, uint32_t *ticks)
{
uint32_t cur_secs, cur_secs2;
cur_secs = readback_mux->time64_secs_rb;
*ticks = readback_mux->time64_ticks_rb;
cur_secs2 = readback_mux->time64_secs_rb;
/* Check for seconds wrap */
if (cur_secs2 != cur_secs) {
/* Decide which seconds reading is correct.
* Here we assume that we're reading fast and time between
* two readings is negligible compared to a 32-bit counter
* wrap time.
*/
if (*ticks < UINT32_MAX/2) {
/* First half of the time - wrap has just happened */
*secs = cur_secs2;
} else {
/* Second half - wrap has not happened yet */
*secs = cur_secs;
}
}
}
int
time64_compare(uint32_t secs1, uint32_t ticks1,
uint32_t secs2, uint32_t ticks2)
{
if (secs1 == secs2) {
if (ticks1 < ticks2) {
return -1;
} else if (ticks1 == ticks2) {
return 0;
} else {
return 1;
}
} else if (secs1 < secs2) {
return -1;
} else {
return 1;
}
}
void
time64_add_ticks(uint32_t *secs, uint32_t *ticks,
uint32_t ticks2)
{
if (UINT32_MAX - *ticks > ticks2) {
*secs += 1;
}
*ticks += ticks2;
}
bool
time64_is_elapsed(uint32_t secs1, uint32_t ticks1,
uint32_t secs2, uint32_t ticks2,
uint32_t ticks_elapsed)
{
time64_add_ticks(&secs1, &ticks1, ticks_elapsed);
return time64_compare(secs1, ticks1, secs2, ticks2) >= 0;
}

42
zpu/lib/time64.h
View File

@@ -1,42 +0,0 @@
/*
* Copyright 2017 Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Operations with time64 counters handling wrapping safely */
/* Read counters */
void
time64_read(uint32_t *secs, uint32_t *ticks);
/* Compare two counters.
* Return -1 if conter 1 is less than counter 2.
* Return 0 if conter 1 is equal counter 2.
* Return 1 if conter 1 is larger than counter 2.
*/
int
time64_compare(uint32_t secs1, uint32_t ticks1,
uint32_t secs2, uint32_t ticks2);
/* Add ticks to a counter */
void
time64_add_ticks(uint32_t *secs, uint32_t *ticks,
uint32_t ticks2);
/* Is a given amount of ticks elapsed? */
bool
time64_is_elapsed(uint32_t secs1, uint32_t ticks1,
uint32_t secs2, uint32_t ticks2,
uint32_t ticks_elapsed);

49
zpu/lib/udp_uart.c
View File

@@ -25,35 +25,24 @@
* Constants
**********************************************************************/
#define MAX_NUM_UARTS 4
#ifndef NUM_UARTS_STORAGE
#error missing definition for NUM_UARTS_STORAGE
#endif
#ifndef UDP_UART_MASK
#error missing definition for UDP_UART_MASK enable mask
#endif
static const size_t num_idle_cyc_b4_flush = 250; //small but lucky number
static const size_t num_idle_cyc_b4_flush = 11; //small but lucky number
/***********************************************************************
* Globals
**********************************************************************/
static uint16_t _base_port;
static int8_t _storage_map[MAX_NUM_UARTS];
#ifdef BOOTLOADER
#define UART_BUF_SZ 16
#else
#define UART_BUF_SZ 128
#endif
typedef struct{
struct socket_address dst;
_AL4 uint8_t buf[UART_BUF_SZ];
_AL4 uint8_t buf[256];
size_t len; //length of buffer
size_t cyc; //idle cycle count
} udp_uart_state_t;
static udp_uart_state_t _states[NUM_UARTS_STORAGE];
static udp_uart_state_t _states[MAX_NUM_UARTS];
/***********************************************************************
* UDP handler for UARTs
@@ -66,20 +55,14 @@ static void handle_uart_data_packet(
if (payload == NULL){
const size_t which = src.port-_base_port;
if (which >= MAX_NUM_UARTS) return;
int8_t idx = _storage_map[which];
if (idx >= NUM_UARTS_STORAGE || idx < 0) return;
_states[idx].dst.port = 0;
_states[which].dst.port = 0;
}
//handle a regular blocking UART write
else{
const size_t which = dst.port-_base_port;
if (which >= MAX_NUM_UARTS) return;
int8_t idx = _storage_map[which];
if (idx >= NUM_UARTS_STORAGE || idx < 0) return;
_states[idx].dst = src;
_states[which].dst = src;
for (size_t i = 0; i < payload_len; i++){
hal_uart_putc((hal_uart_name_t)which, (int)payload[i]);
}
@@ -91,20 +74,11 @@ static void handle_uart_data_packet(
**********************************************************************/
void udp_uart_init(const uint16_t base_port){
_base_port = base_port;
for(size_t i = 0, k = 0; (i < MAX_NUM_UARTS) && (k < NUM_UARTS_STORAGE); i++){
if (((UDP_UART_MASK) & (1 << i)) == 0) {
_storage_map[i] = -1;
continue;
}
_storage_map[i] = k;
_states[k].dst.port = 0; //reset to null port
_states[k].len = 0;
_states[k].cyc = 0;
for(size_t i = 0; i < MAX_NUM_UARTS; i++){
_states[i].dst.port = 0; //reset to null port
_states[i].len = 0;
_states[i].cyc = 0;
register_udp_listener(_base_port+i, handle_uart_data_packet);
++k;
}
}
@@ -113,11 +87,10 @@ void udp_uart_init(const uint16_t base_port){
**********************************************************************/
void udp_uart_poll(void){
for (size_t i = 0; i < MAX_NUM_UARTS; i++){
int8_t idx = _storage_map[i];
if (idx >= NUM_UARTS_STORAGE || idx < 0) continue;
if (((UDP_UART_MASK) & (1 << i)) == 0) continue;
bool newline = false;
udp_uart_state_t *state = &_states[idx];
udp_uart_state_t *state = &_states[i];
//read all characters we can without blocking
for (size_t j = state->len; j < sizeof(_states[0].buf); j++){

31
zpu/umtrx/CMakeLists.txt
View File

@@ -19,33 +19,28 @@
INCLUDE(${CMAKE_SOURCE_DIR}/lib/CMakeLists.txt)
INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
SET(MIN_STACK 1300)
ADD_DEFINITIONS(-DUSRP2P)
ADD_DEFINITIONS(-DUDP_UART_MASK=2 -DNUM_UARTS_STORAGE=1) #GPS=UART1 streaming enabled
ADD_DEFINITIONS(-DUDP_UART_MASK=2) #GPS=UART1 streaming enabled
SET(libumtrxfw_FILES
ADD_LIBRARY(libumtrxfw STATIC
${COMMON_SRCS}
${CMAKE_SOURCE_DIR}/umtrx/spif.c
${CMAKE_SOURCE_DIR}/umtrx/spi_flash.c
${CMAKE_SOURCE_DIR}/umtrx/spi_flash_read.c
${CMAKE_SOURCE_DIR}/umtrx/bootloader_utils.c
${CMAKE_SOURCE_DIR}/umtrx/ethernet.c
${CMAKE_SOURCE_DIR}/umtrx/xilinx_s3_icap.c
${CMAKE_SOURCE_DIR}/umtrx/xilinx_s6_icap.c
${CMAKE_SOURCE_DIR}/umtrx/udp_fw_update.c
${CMAKE_SOURCE_DIR}/umtrx/u2p_init.c
spif.c
spi_flash.c
spi_flash_read.c
bootloader_utils.c
ethernet.c
xilinx_s3_icap.c
xilinx_s6_icap.c
udp_fw_update.c
u2p_init.c
)
# ADD_LIBRARY(libumtrxfw STATIC ${libumtrxfw_FILES})
ADD_SUBDIRECTORY(bootloader)
########################################################################
SET(GEN_OUTPUTS_BIN_SIZE 0x3fff)
ADD_EXECUTABLE(umtrx_txrx_uhd.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c ${libumtrxfw_FILES})
# TARGET_LINK_LIBRARIES(umtrx_txrx_uhd.elf libumtrxfw)
ADD_EXECUTABLE(umtrx_txrx_uhd.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c)
TARGET_LINK_LIBRARIES(umtrx_txrx_uhd.elf libumtrxfw)
GEN_OUTPUTS(umtrx_txrx_uhd.elf)
TEST_STACK_SIZE(umtrx_txrx_uhd.elf ${MIN_STACK})

7
zpu/umtrx/bootloader/CMakeLists.txt
View File

@@ -33,13 +33,10 @@ MACRO(GEN_RMI target)
ENDMACRO(GEN_RMI)
########################################################################
ADD_EXECUTABLE(bootloader.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c)
ADD_DEFINITIONS(-DUSRP2P)
ADD_DEFINITIONS(-DBOOTLOADER)
ADD_EXECUTABLE(bootloader.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c ${libumtrxfw_FILES})
# TARGET_LINK_LIBRARIES(bootloader.elf libumtrxfw)
TARGET_LINK_LIBRARIES(bootloader.elf libumtrxfw)
SET(GEN_OUTPUTS_BIN_SIZE 0x3fff)
GEN_OUTPUTS(bootloader.elf)
GEN_RMI(bootloader.bin)
TEST_STACK_SIZE(bootloader.elf ${MIN_STACK})

22
zpu/umtrx/bootloader_utils.c
View File

@@ -40,10 +40,14 @@ int is_valid_fpga_image(uint32_t addr) {
}
int is_valid_fw_image(uint32_t addr) {
static const uint8_t fwheader[2] = {0x0b, 0x0b}; //just lookin for a jump to anywhere located at the reset vector
uint8_t buf[2];
spi_flash_read(addr, 2, buf);
return memcmp(buf, fwheader, 2) == 0;
static const uint8_t fwheader[] = {0x0b, 0x0b, 0x0b, 0x0b}; //just lookin for a jump to anywhere located at the reset vector
//printf("is_valid_fw_image(): starting with addr=%x...\n", addr);
uint8_t buf[12];
spi_flash_read(addr, 4, buf);
//printf("is_valid_fw_image(): read ");
//for(int i = 0; i < 5; i++) printf("%x ", buf[i]);
//printf("\n");
return memcmp(buf, fwheader, 4) == 0;
}
void start_program(void)
@@ -67,14 +71,14 @@ void do_the_bootload_thing(void) {
set_safe_booted_flag(0); //haven't booted yet
if(BUTTON_PUSHED) { //see memory_map.h
puts("Starting UmTRX in safe mode.");
puts("Starting UmTRX in safe mode. Loading safe firmware.");
return;
}
if(!production_image) {
puts("Checking for valid production FPGA image...");
if(is_valid_fpga_image(PROD_FPGA_IMAGE_LOCATION_ADDR)) {
puts("Valid production FPGA image found, booting..");
puts("Valid production FPGA image found. Attempting to boot.");
set_safe_booted_flag(1);
mdelay(300); //so serial output can finish
#ifdef SPARTAN6
@@ -89,10 +93,10 @@ void do_the_bootload_thing(void) {
if(is_valid_fw_image(PROD_FW_IMAGE_LOCATION_ADDR)) {
puts("Valid production firmware found. Loading...");
spi_flash_read(PROD_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE);
puts("Starting image...");
puts("Finished loading. Starting image.");
mdelay(300);
start_program();
puts("ERROR: Return from main!");
puts("ERROR: Return from main program! This should never happen!");
//if this happens, though, the safest thing to do is reboot the whole FPGA and start over.
mdelay(300);
#ifdef SPARTAN6
@@ -102,6 +106,6 @@ void do_the_bootload_thing(void) {
#endif
return;
}
puts("No valid production firmware found!");
puts("No valid production firmware found. Falling through to built-in firmware.");
#endif
}

4
zpu/umtrx/spi_flash_read.c
View File

@@ -43,7 +43,7 @@ size_t spi_flash_log2_memory_size(void)
}
if (_spi_flash_log2_memory_size < 22 ||
_spi_flash_log2_memory_size > 24 ){
printf("\nWrong flash size: %d Achtung!\n", (int)_spi_flash_log2_memory_size);
printf("\nWrong flash size: %d Achtung!\n", _spi_flash_log2_memory_size);
abort();
}
return _spi_flash_log2_memory_size;
@@ -51,7 +51,7 @@ size_t spi_flash_log2_memory_size(void)
size_t spi_flash_log2_sector_size(void)
{
static const unsigned char log2_sector_size[3] = {
static unsigned char log2_sector_size[3] = {
16, /* M25P32 */
16, /* M25P64 */
18, /* M25P128 */