Alexander Chemeris
064de45a45
images: Checking in a sligtly more optimal production ZPU image.
...
My version of the ZPU compiler genrates more optimal code than Sergey's probably
because it's a purely C compiler vs a combined C/C++ one Sergey has. So this
version of production ZPU image has 1829 bytes available for stack, while
Sergey's had only 1764 bytes. Given we're not sure how much stack do we really
need, it's better to have more. My bootloader has 1507 bytes avialable for
stack, while Sergey's has only 1442.
2017-08-04 15:53:42 +03:00
Sergey Kostanbaev
e03e43151b
fpga: update default bootloader, increase minor version
2017-08-04 15:42:20 +03:00
Sergey Kostanbaev
3dac709c49
add map config for latest successful timing build
2016-06-30 16:41:07 +03:00
Josh Blum
57d5ca4b51
fpga: simplify spi setting regs with generate loop
2015-07-29 19:21:28 -07:00
Josh Blum
b78ceeb9b1
fpga: connect both spi settings drivers
2015-07-29 01:59:54 -07:00
Josh Blum
fcd92d8f50
fpga: use axi stream spi core (still single dest)
2015-07-28 16:32:17 -07:00
Josh Blum
2727f62ab8
fpga: created axi stream controled spi core
2015-07-28 16:31:29 -07:00
Josh Blum
41b93944a0
fpga: move tx frontend mux between DSP and corrections module
...
On the RX side, the same mux is between the corrections and the DSP.
However, for TX, this was between the DAC and corrections module,
leading to the host code setting the wrong corrections when the
channel 0 was set to frontend mapping "B:0".
This fixes the issue with the tx iq calibration utility.
A new fpga image is checked in and compat minor bumped.
2015-05-28 17:33:00 -04:00
Josh Blum
453caf23e8
umtrx: updated binaries after bootloader work
2015-04-27 17:21:01 -07:00
Josh Blum
0a3dd778d0
umtrx: slow down icap clock, this image resets reliably
...
Looks like icap clk from the pll is shared with the frontend clock.
So instead I opted to divide the icap clk down inside s6_icap_wb.v.
The image checked in reset reliably after many trials,
which is a good sign that this may be an acceptable fix.
2015-04-01 00:45:00 -07:00
Josh Blum
924dcf8d8a
umtrx: s2 slave unused, fix comment
2015-03-17 12:05:23 -07:00
Sergey Kostanbaev
db0d59f936
update fpga & zpu images
2015-03-12 21:01:44 +03:00
Sergey Kostanbaev
a37e4c74de
fpga: fix DCSYNC clock to 541.66 kHz
2015-03-12 20:35:25 +03:00
Sergey Kostanbaev
064b7bcf28
Add DCSYNC for DC/DC. Not tested since I don't have an oscilloscope.
2014-12-21 22:35:33 +03:00
Sergey Kostanbaev
e08b40758a
Add PA control logic
2014-12-21 13:07:20 +03:00
Josh Blum
197e2f01f9
umtrx: added net reset for fw/fpga boot
2014-10-27 20:21:26 -04:00
Josh Blum
1553c302e9
umtrx: 4DDC leds reversed
2014-10-27 17:32:04 -04:00
Josh Blum
195da695ec
umtrx: remap LEDS, regular and 4DDC cases -- needs test
2014-10-27 10:19:54 -04:00
Josh Blum
fc309a340f
umtrx: deleted build for unused revision
2014-10-27 10:19:07 -04:00
Josh Blum
3741147c33
umtrx: move buffering + gateway to rx chain
2014-10-15 17:22:45 -07:00
Josh Blum
1bb4b3f9a3
umtrx: remap dsps, add rx buffering
2014-10-15 13:49:03 -07:00
Josh Blum
13901ed852
umtrx: fpga build for 4DDC and arbitrary DSP support
2014-10-14 21:51:25 -07:00
Josh Blum
7182e3d199
umtrx: init frontend muxes to IQ -- fixes TX mux
2014-07-10 08:34:21 -07:00
Josh Blum
52dcddfbcd
umtrx: fix led mux and dac mux from last commits
2014-05-28 09:20:10 -07:00
Josh Blum
be60c6c249
umtrx: fixup mux typo
2014-05-27 14:04:41 -07:00
Josh Blum
a35ef2ca0c
umtrx: added tx mux switch based on subdev spec
2014-05-27 12:08:13 -07:00
Josh Blum
3cbeef064d
umtrx: strobe adcs from same signal for DSP alignment
2014-04-21 18:27:43 -07:00
Josh Blum
c9e8839e09
umtrx: fix typo in settings bus assign
2014-04-21 16:40:40 -07:00
Josh Blum
640043a6e3
umtrx: external rx fe switch for quad dsp support -- has issues
2014-04-21 11:02:56 -07:00
Josh Blum
bee6934762
umtrx: switch to timed spi core
2014-04-20 23:37:57 -07:00
Josh Blum
7b7b8d5801
umtrx: renamed u2plus_core.v to umtrx_core.v
2014-04-20 19:15:43 -07:00
Josh Blum
a7d5cac2c9
umtrx: resets and clears when IMCP disconnect -- UDP dest not reachable
2014-04-20 10:56:12 -07:00
Josh Blum
ef41d7c577
umtrx: misc cleanup from last commit
2014-04-20 08:34:57 -07:00
Josh Blum
92b3cbfc2e
umtrx: fix prot framer bug for gen_context_pkt
2014-04-19 22:43:28 -07:00
Josh Blum
442f251f51
umtrx: tx work, fix prot framing, remap stuff
2014-04-19 21:40:00 -07:00
Josh Blum
565ced2732
umtrx: lms reset gets its own register
2014-04-19 16:35:42 -07:00
Josh Blum
4bf197085c
umtrx: allocate constants for framers, sids, exc
2014-04-19 12:34:18 -07:00
Josh Blum
5eee7ccbd7
umtrx: protocol framer is 2x wide now, 8 entries
2014-04-19 11:10:59 -07:00
Josh Blum
d660c361ed
umtrx: protoframer gets dedicted settings bus
2014-04-19 10:41:44 -07:00
Josh Blum
ecd4cef37d
umtrx: tie in fifo ctrl to settings bus
2014-04-19 09:41:38 -07:00
Josh Blum
4620ad044c
umtrx: work in settings fifo integration
2014-04-18 22:52:01 -07:00
Josh Blum
8cfcecc427
umtrx: added back dispatcher drop vs to cpu case
2014-04-18 20:50:23 -07:00
Josh Blum
e816a55ee2
umtrx: work on wider router and dispatcher + fw changes to match -- not tested
2014-04-18 18:41:23 -07:00
Josh Blum
27422503b8
umtrx: added axi demux
2014-04-18 18:39:51 -07:00
Josh Blum
59539e50ff
umtrx: added axi many muxes for new router
2014-04-18 16:19:31 -07:00
Josh Blum
be396dbd31
umtrx: began work on umtrx router to support ctrl fifo + more
2014-04-18 16:18:35 -07:00
Josh Blum
c4216f41d7
umtrx: misc files created by fpga build
2014-04-18 13:51:44 -07:00
Josh Blum
0a52a45e1b
umtrx: removed unused stuff
2014-04-18 13:51:28 -07:00
Josh Blum
54030551e3
umtrx: need pkt gate for max rate bursting in eth tx chain
2014-04-18 12:22:59 -07:00
Josh Blum
b8b5319c6d
umtrx: added axi fifo2clk, didnt fix the issue though
2014-04-17 22:24:32 -07:00
